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MoS2 quantum dots/AlGaN nanowire heterostructure-based photodetectors for solar-blind photodetection and optical communication
Menglong Wang, Wei Chen, Xin Liu, Wengang Gu, Yang Li, Xudong Yang, Haiding Sun
, Available online  

doi: 10.1088/1674-4926/25090026

Solar-blind ultraviolet photodetectors (UV PDs), capable of detecting UV radiation without interference from sunlight, have attracted significant interest. Herein, we propose a 0D/1D heterostructure for UV PDs, which was fabricated by spin-coating MoS2 quantum dots onto p-AlGaN nanowires. The device achieves a high responsivity of 175.5 mA/W and a fast response speed of 83 ms at 250 nm illumination under self-powered mode, which improved nearly 1235% and 521% after MoS2 decoration, respectively. These improvements can be attributed to the type-II heterostructure formed between p-AlGaN and MoS2, which facilitates enhanced charge separation and carrier transport. Later, we demonstrate the implementation of this device in optical communication, achieving high-accuracy transmission of “GaN” ASCII code signals. Such a 0D/1D heterostructure provides an effective strategy for high-performance solar-blind UV PD.

Solar-blind ultraviolet photodetectors (UV PDs), capable of detecting UV radiation without interference from sunlight, have attracted significant interest. Herein, we propose a 0D/1D heterostructure for UV PDs, which was fabricated by spin-coating MoS2 quantum dots onto p-AlGaN nanowires. The device achieves a high responsivity of 175.5 mA/W and a fast response speed of 83 ms at 250 nm illumination under self-powered mode, which improved nearly 1235% and 521% after MoS2 decoration, respectively. These improvements can be attributed to the type-II heterostructure formed between p-AlGaN and MoS2, which facilitates enhanced charge separation and carrier transport. Later, we demonstrate the implementation of this device in optical communication, achieving high-accuracy transmission of “GaN” ASCII code signals. Such a 0D/1D heterostructure provides an effective strategy for high-performance solar-blind UV PD.
Optimization and defect control in photoresist etch back processes for advanced semiconductor technologies
Ting Lei, Zhehong Liu, Zhiwen Liu, Guangjie Xue, Chun Sun, Jun Zhou, Xiangshui Miao
, Available online  

doi: 10.1088/1674-4926/25070024

The introduction of high-k/metal gate (HK/MG) technology enables independent tuning of N-type Metal-Oxide-Semiconductor (NMOS) and P-type Metal-Oxide-Semiconductor (PMOS) threshold voltages, facilitating advanced nodes and improving overall chip performance. However, severe pattern loading effects during PMOS device fabrication pose challenges in Dummy Poly removal. This work reports the optimization of the Photoresist Etch Back (PREB) process, providing a wider process window for subsequent AL CMP. By tuning the PR coating uniformity to 1.6% and applying four-zone Electrostatic Chuck (ESC) temperature control, the wafer-level uniformities of PR, SiN, and SiO2 were reduced to 6.3%, 2.3%, and 5.1%, respectively. An optimized over etch (OE) recipe with a high selectivity of PR : SiN : SiO2 ≈ 1 : 1 : 6 effectively balanced gate height loading between N- and PMOS regions. Furthermore, precise EB1 time tuning enabled defect removal, while advanced KLA inspection ensured early detection of critical failure modes. Collectively, these measures establish a robust and stable PREB process for advanced logic device fabrication.

The introduction of high-k/metal gate (HK/MG) technology enables independent tuning of N-type Metal-Oxide-Semiconductor (NMOS) and P-type Metal-Oxide-Semiconductor (PMOS) threshold voltages, facilitating advanced nodes and improving overall chip performance. However, severe pattern loading effects during PMOS device fabrication pose challenges in Dummy Poly removal. This work reports the optimization of the Photoresist Etch Back (PREB) process, providing a wider process window for subsequent AL CMP. By tuning the PR coating uniformity to 1.6% and applying four-zone Electrostatic Chuck (ESC) temperature control, the wafer-level uniformities of PR, SiN, and SiO2 were reduced to 6.3%, 2.3%, and 5.1%, respectively. An optimized over etch (OE) recipe with a high selectivity of PR : SiN : SiO2 ≈ 1 : 1 : 6 effectively balanced gate height loading between N- and PMOS regions. Furthermore, precise EB1 time tuning enabled defect removal, while advanced KLA inspection ensured early detection of critical failure modes. Collectively, these measures establish a robust and stable PREB process for advanced logic device fabrication.
High-speed single-mode 850 nm vertical-cavity surface-emitting laser
Si-Cong Tian
, Available online  

doi: 10.1088/1674-4926/25090008

A high-speed single-mode vertical-cavity surface-emitting laser (VCSEL) is one of the most important light sources for optical interconnects in data centers. Single-mode VCSEL can improve the transmission distance. In this letter, we demonstrate a single-mode 850nm VCSEL with a bit rate of 60 Gb/s under NRZ modulation and 104 Gb/s under PAM4 modulation across a 100 m length of OM5 fiber, without the need for equalization or a filter. In addition, by using optical injection locking, the 3dB bandwidth is enhanced to 68.5 GHz.

A high-speed single-mode vertical-cavity surface-emitting laser (VCSEL) is one of the most important light sources for optical interconnects in data centers. Single-mode VCSEL can improve the transmission distance. In this letter, we demonstrate a single-mode 850nm VCSEL with a bit rate of 60 Gb/s under NRZ modulation and 104 Gb/s under PAM4 modulation across a 100 m length of OM5 fiber, without the need for equalization or a filter. In addition, by using optical injection locking, the 3dB bandwidth is enhanced to 68.5 GHz.