J. Semicond. > Volume 30 > Issue 10 > Article Number: 104003

Improvements on high voltage performance of power static induction transistors

Wang Yongshun , Li Hairong , Wang Ziting and Li Siyuan

+ Author Affiliations + Find other works by these authors


Abstract: A novel structure for designing and fabricating a power static induction transistor (SIT) with excellent high breakdown voltage performance is presented. The active region of the device is designed to be surrounded by a deep trench to cut off the various probable parasitical effects that may degrade the device performance, and to avoid the parallel-current effect in particular. Three ring-shape junctions (RSJ) are arranged around the gate junction to reduce the electric field intensity. It is important to achieve maximum gate–source breakdown voltage BVGS, gate–drain breakdown voltage BVGD and blocking voltage for high power application. A number of technological methods to increase BVGD and BVGS are presented. The BVGS of the power SIT has been increased to 110 V from a previous value of 50–60 V, and the performance of the power SIT has been greatly improved. The optimal distance between two adjacent ring-shape junctions and the trench depth for the maximum BVGS of the structure are also presented.

Key words: static induction transistor parasitic effect breakdown voltage deep trench


Wang Yongshun, Wu Rong, Liu Chunjuan, Li Siyuan. Improvements on High Current Performance of StaticInduction Transistor. J. Semicond., 2007, 28(8): 1192.


Cheng Jianbing, Zhang Bo, Li Zhaoji. Breakdown Voltage Characteristics of LDMOS with a Full Depletion Floating Buried Layer. J. Semicond., 2008, 29(2): 344.


Zhang Bo, Duan Baoxing, Li Zhaoji. Breakdown Voltage Analysis of a REBULF LDMOS Structurewith an n+-Floating Layer. J. Semicond., 2006, 27(4): 730.


Duan Baoxing, Zhang Bo, Li Zhaoji. A Breakdown Voltage Model of a PSOI Structure with a p-Type Buried Layer. J. Semicond., 2005, 26(11): 2149.


Tang Ying, Liu Su, Li Siyuan, Wu Rong, Chang Peng. A Novel Structure for a Static Induction Transistor. J. Semicond., 2007, 28(6): 918.


Yu Zongguang, Liu Zhan, Wang Guozhang, Xu Ziming. An ADI Method for the Breakdown Voltage Analysis of Thin-Film SOI RESURF Structure with the High-Order Compact Finite Difference. J. Semicond., 2006, 27(2): 354.


Wu Lijuan, Hu Shengdong, Zhang Bo, Li Zhaoji. A new SOI high voltage device based on E-SIMOX substrate. J. Semicond., 2010, 31(4): 044008. doi: 10.1088/1674-4926/31/4/044008


Qing Xu, Xiaorong Luo, Kun Zhou, Ruichao Tian, Jie Wei, Yuanhang Fan, Bo Zhang. Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect. J. Semicond., 2015, 36(2): 024010. doi: 10.1088/1674-4926/36/2/024010


Luo Xiaorong, Li Zhaoji, Zhang Bo, Guo Yufeng, Tang Xinwei. A Novel Structure and Its Breakdown Mechanism of a SOI High Voltage Device with a Shielding Trench. J. Semicond., 2005, 26(11): 2154.


Yang Liu, Changchun Chai, Chunlei Shi, Qingyang Fan, Yuqian Liu. Optimization design on breakdown voltage of AlGaN/GaN high-electron mobility transistor. J. Semicond., 2016, 37(12): 124002. doi: 10.1088/1674-4926/37/12/124002


, , , , . Space Charges Effect of Static Induction Transistor. J. Semicond., 2005, 26(3): 423.


Hu Xiarong, Zhang Bo, Luo Xiaorong, Li Zhaoji. Universal trench design method for a high-voltage SOI trench LDMOS. J. Semicond., 2012, 33(7): 074006. doi: 10.1088/1674-4926/33/7/074006


Ye Jun, Fu Daping, Luo Bo, Zhao Yuanyuan, Qiao Ming, Zhang Bo. A novel TFS-IGBT with a super junction floating layer. J. Semicond., 2010, 31(11): 114008. doi: 10.1088/1674-4926/31/11/114008


Luo Xiaorong, Zhang Bo, Li Zhaoji, Tang Xinwei. A Novel SOI High Voltage Device Structure with a Partial Locating Charge Trench. J. Semicond., 2006, 27(1): 115.


Liu Jun, Sun Lingling, Xu Xiaojun. RF-CMOS Modeling:Parasitic Analysis for MOST On-Wafer Test Structure. J. Semicond., 2007, 28(2): 246.


Qiao Ming, Zhou Xianda, Duan Mingwei, Fang Jian, Zhang Bo, Li Zhaoji. Breakdown Characteristic of Multiregion Double RESURF LDMOS with High Voltage Interconnection. J. Semicond., 2007, 28(9): 1428.


Duan Baoxing, Zhang Bo, Li Zhaoji. Breakdown Voltage Analysis for a Double Step Buried Oxide SOI Structure. J. Semicond., 2006, 27(5): 886.


Li Qi, Zhu Jinluan, Wang Weidong, Yue Hongwei, Jin Liangnian. A novel high-voltage device structure with an N+ ring in substrate and the breakdown voltage model. J. Semicond., 2011, 32(12): 124005. doi: 10.1088/1674-4926/32/12/124005


Ma Juncai, Zhang Jincheng, Xue Junshuai, Lin Zhiyu, Liu Ziyang, Xue Xiaoyong, Ma Xiaohua, Hao Yue. Characteristics of AlGaN/GaN/AlGaN double heterojunction HEMTs with an improved breakdown voltage. J. Semicond., 2012, 33(1): 014002. doi: 10.1088/1674-4926/33/1/014002


Chen Wanjun, Zhang Bo, Li Zhaoji. Realizing High Breakdown Voltage SJ-LDMOS on Bulk Silicon Using a Partial n-Buried Layer. J. Semicond., 2007, 28(3): 355.


Advanced Search >>


Wang Y S, Li H R, Wang Z T, Li S Y. Improvements on high voltage performance of power static induction transistors[J]. J. Semicond., 2009, 30(10): 104003. doi: 10.1088/1674-4926/30/10/104003.

Export: BibTex EndNote

Article Metrics

Article views: 2396 Times PDF downloads: 2145 Times Cited by: 0 Times


Manuscript received: 18 August 2015 Manuscript revised: 09 May 2009 Online: Published: 01 October 2009

Email This Article

User name: