J. Semicond. > Volume 30 > Issue 10 > Article Number: 106003

A wafer-level 3D packaging structure with Benzocyclobutene as a dielectric for multichip module fabrication

Geng Fei , Ding Xiaoyun , Xu Gaowei and Luo Le

+ Author Affiliations + Find other works by these authors


Abstract: A new wafer-level 3D packaging structure with Benzocyclobutene (BCB) as interlayer dielectrics (ILDs) for multichip module fabrication is proposed for application in the Ku-band wave. The packaging structure consists of two layers of BCB films and three layers of metallized films, in which the monolithic microwave IC (MMIC), thin film resistors, striplines and microstrip lines are integrated. Wet etched cavities fabricated on the silicon substrate are used for mounting active and passive components. BCB layers cover the components and serve as ILDs for interconnections. Gold bumps are used as electric interconnections between different layers, which eliminates the need to prepare vias by costly dry etching and deposition processes. In order to get high-quality BCB films for the subsequent chemical mechanical planarization (CMP) and multilayer metallization processes, the BCB curing profile is optimized and the roughness of the BCB film after the CMP process is kept lower than 10 nm. The thermal, mechanical and electrical properties of the packaging structure are investigated. The thermal resistance can be controlled below 2 ℃/W. The average shear strength of the gold bumps on the BCB surface is around 70 N/mm2. The performances of MMIC and interconnection structure at high frequencies are optimized and tested. The S-parameters curves of the packaged MMIC shift slightly showing perfect transmission character. The insertion loss change after the packaging process is less than 1 dB range at the operating frequency and the return loss is less than –8 dB from 10 to 15 GHz.

Key words: wafer-level


Linsong Zhou, Haibo Rao, Wei Wang, Xianlong Wan, Junyuan Liao, Xuemei Wang, Da Zhou, Qiaolin Lei. Self-adaptive phosphor coating technology for wafer-level scale chip packaging. J. Semicond., 2013, 34(5): 054010. doi: 10.1088/1674-4926/34/5/054010


Zhiqiang Fang, Xu Mao, Jinling Yang, Fuhua Yang. Low temperature Sn-rich Au-Sn wafer-level bonding. J. Semicond., 2013, 34(10): 106001. doi: 10.1088/1674-4926/34/10/106001


Cao Yuhan, Luo Le. Wafer level hermetic packaging based on Cu–Sn isothermal solidification technology. J. Semicond., 2009, 30(8): 086001. doi: 10.1088/1674-4926/30/8/086001


Qiao Ming, Fang Jian, Li Zhaoji, Zhang Bo. HVIC with Coupled Level Shift Structure. J. Semicond., 2006, 27(11): 2040.


Zhang Xiaoying, Chen Songyan, Lai Hongkai, Li Cheng, Yu Jinzhong. Low-Temperature Wafer-to-Wafer Bonding Using Intermediate Metals. J. Semicond., 2007, 28(2): 213.


Guo Debo, Liang Meng, Fan Manning, Liu Zhiqiang, Wang Liangchen, Wang Guohong. Study of AIGalnP/Si Wafer Bonding. J. Semicond., 2007, 28(S1): 558.


Bo Peng, Deguang Zheng, Yue Yu. Method to remove wafer surface particles. J. Semicond., 2017, 38(9): 096004. doi: 10.1088/1674-4926/38/9/096004


Tan Kaizhou, Zhang Jing, Xu Shiliu, Zhang Zhengfan, Yang Yonghui, Chen Jun, Liang Tao. Study of hybrid orientation structure wafer. J. Semicond., 2011, 32(6): 063002. doi: 10.1088/1674-4926/32/6/063002


Wang Chao, Zhang Yimen, Zhang Yuming, Wang Yuehu, Xu Daqing. Deep Level Transient Fourier Spectroscopy and Photoluminescence of Vanadium Acceptor Level in n-Type 4H-SiC. J. Semicond., 2008, 29(2): 240.


Ken K. Chin, Zimeng Cheng. Semiconductor steady state defect effective Fermi level and deep level transient spectroscopy depth profiling. J. Semicond., 2016, 37(9): 092003. doi: 10.1088/1674-4926/37/9/092003


Jiang Shouzhen, Xu Xian'gang, Li Juan, Chen Xiufang, Wang Yingmin, Ning Li'na, Hu Xiaobo, Wang Jiyang, Jiang Minhua. Recent Progress in SiC Monocrystal Growth and Wafer Machining. J. Semicond., 2007, 28(5): 810.


Men Yanwu, Zhang Hui, Zhou Kai, Ye Peiqing. Wafer back pressure control and optimization in the CMP process. J. Semicond., 2011, 32(12): 126002. doi: 10.1088/1674-4926/32/12/126002


Zhang Kailiang, Song Zhitang, Zhong Min, Zheng Mingjie, Feng Songlin. Double Side Fine CMP of Silicon Wafer. J. Semicond., 2006, 27(S1): 396.


Ma Canghai, Liao Guanglan, Shi Tielin, Tang Zirong, Liu Shiyuan, Nie Lei, Lin Xiaohui. Wafer Direct Bonding Based on UV Exposure. J. Semicond., 2008, 29(7): 1369.


Sui Xiaohong, Chen Hongda. Microfabrication and Evaluation of a Silicon MicroelectrodeBased on SOI Wafer. J. Semicond., 2008, 29(11): 2169.


Li Xiujuan, Jin Zhuji, Kang Renke, Guo Dongming, Su Jianxiu. Corrosive Effect of Slurry Inhibitor on Copper Wafer. J. Semicond., 2005, 26(11): 2259.


Ma Ziwen, Tang Zirong, Liao Guanglan, Shi Tielin. Criterion of Microroughness for Self-Propagating Wafer Bonding. J. Semicond., 2007, 28(3): 465.


Minzeng Li, Fule Li, Chun Zhang, Zhihua Wang. Pixel-level A/D conversion using voltage reset technique. J. Semicond., 2014, 35(11): 115009. doi: 10.1088/1674-4926/35/11/115009


Wenlong Jiao, Weizheng Yuan, Honglong Chang. System level simulation of a micro resonant accelerometer with geometric nonlinear beams. J. Semicond., 2015, 36(10): 104007. doi: 10.1088/1674-4926/36/10/104007


Zhang Yufeng, Liu Xiaowei, Chen Weiping. System-Level Modeling and Simulation of Force-Balance MEMS Accelerometers. J. Semicond., 2008, 29(5): 917.


Advanced Search >>


Geng F, Ding X Y, Xu G W, Luo L. A wafer-level 3D packaging structure with Benzocyclobutene as a dielectric for multichip module fabrication[J]. J. Semicond., 2009, 30(10): 106003. doi: 10.1088/1674-4926/30/10/106003.

Export: BibTex EndNote

Article Metrics

Article views: 2707 Times PDF downloads: 2844 Times Cited by: 0 Times


Manuscript received: 18 August 2015 Manuscript revised: 13 May 2009 Online: Published: 01 October 2009

Email This Article

User name: