J. Semicond. > Volume 30 > Issue 12 > Article Number: 125007

A bootstrapped switch employing a new clock feed-through compensation technique

Wu Xiaofeng , Liu Hongxia , Su Li , Hao Yue , Li Di and Hu Shigang

+ Author Affiliations + Find other works by these authors


Abstract: Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.

Key words: bootstrapped switch clock feed-through compensation delay path match设计优化


Hu Xiaoyu, Zhou Yumei. A CMOS Sampling Switch for 14bit 50MHz Pipelined A/D Converter. J. Semicond., 2007, 28(9): 1488.


Xiaoshi Zhu, Chixiao Chen, Jialiang Xu, Fan Ye, Junyan Ren. An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling. J. Semicond., 2013, 34(3): 035003. doi: 10.1088/1674-4926/34/3/035003


Nan Zhao, Qi Wei, Huazhong Yang, Hui Wang. A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR. J. Semicond., 2014, 35(9): 095009. doi: 10.1088/1674-4926/35/9/095009


Wang Junqian, Yang Haifeng, Wei Rui, Xu Jun, Ren Junyan. A fourth-order bandwidth-reconfigurable delta–sigma modulator for audio applications. J. Semicond., 2012, 33(7): 075002. doi: 10.1088/1674-4926/33/7/075002


Sen Yue, Yiqiang Zhao, Ruilong Pang, Yun Sheng. A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC. J. Semicond., 2014, 35(5): 055009. doi: 10.1088/1674-4926/35/5/055009


Beichen Zhang, Bingbing Yao, Liyuan Liu, Jian Liu, Nanjian Wu. High power-efficient asynchronous SAR ADC for IoT devices. J. Semicond., 2017, 38(10): 105001. doi: 10.1088/1674-4926/38/10/105001


Long Shanli, Shi Longxing, Wu Jianhui, Wang Pei. A 1.8V 10bit 100Msps Pipelined Analog to Digital Converter. J. Semicond., 2008, 29(5): 923.


Yutong Zhang, Bei Chen, Heping Ma. A sample and hold circuit for pipelined ADC. J. Semicond., 2018, 39(11): 115002. doi: 10.1088/1674-4926/39/11/115002


Guowei Han, Chaowei Si, Jin Ning, Weiwei Zhong, Guosheng Sun, Yongmei Zhao, Fuhua Yang. Feed-through cancellation of a MEMS filter using the difference method and analysis of the induced notch. J. Semicond., 2013, 34(4): 045006. doi: 10.1088/1674-4926/34/4/045006


Guan Xuguang, Zhou Duan, Yang Yintang. Optimization design of a full asynchronous pipeline circuit based on null convention logic. J. Semicond., 2009, 30(7): 075010. doi: 10.1088/1674-4926/30/7/075010


Yang Bin, Yin Xiumei, Yang Huazhong. A High-Speed High-Resolution Sample-and-Hold Circuit. J. Semicond., 2007, 28(10): 1642.


Ye Qiang, Liu Jie, Yuan Bing, Lai Xinquan, Liu Ning. On-chip frequency compensation with a dual signal path operational transconductance amplifier for a voltage mode control DC/DC converter. J. Semicond., 2012, 33(4): 045006. doi: 10.1088/1674-4926/33/4/045006


Zonghua Zheng, Lingling Sun, Jun Liu, Shengzhou Zhang. A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch. J. Semicond., 2016, 37(1): 015001. doi: 10.1088/1674-4926/37/1/015001


Dongfang Pan, Feng Zhang, Lu Huang, Jinliang Li. A common-gate bootstrapped CMOS rectifier for VHF isolated DC-DC converter. J. Semicond., 2017, 38(5): 055002. doi: 10.1088/1674-4926/38/5/055002


Ning Ning, Yu Qi, Wang Xiangzhan, Dai Guanghao, Liu Yuan, Yang Mohua. A Novel Clock Feedthrough Frequency Compensation forFast-Settling of Folded-Cascode OTA. J. Semicond., 2006, 27(10): 1737.


Huang Jiwei, Wang Zhigong. Research and Design of SPDT RF MEMS Switch. J. Semicond., 2007, 28(4): 604.


Jia Cuiping, Dong Wei, Zhou Jingran, Liu Caixia, Zang Huidong, Xuan Wei, Xu Baokun, Chen Weiyou. Fabrication of 8×8 MEMS Optical Switch Array. J. Semicond., 2006, 27(S1): 343.


Wang Xinmei, Shi Wei, Qu Guanghui, Tian Liqiang. Transient Characteristics of a Nonlinear GaAs Photoconductive Semiconductor Switch. J. Semicond., 2008, 29(6): 1108.


Chen Baoqin, Liu Ming, Xu Qiuxia, Xue Lijun, Li Jinru, Tang Yueke, Zhao Min, Liu Zhuming, Wang Deqiang, Ren Liming, Hu Yong, Long Shibing, , Lu Jing, Yang Qinghua, Zhang Lihui. Match and Mixed Lithography Technology Between E-Beam Lithography System and Optical Lithography System. J. Semicond., 2006, 27(S1): 1.


Zhang Jianwei, Ye Yizheng, Liu Binda, Lan Jinbao. A cascaded charge-sharing technique for an EDP-efficient match-line design in CAMs. J. Semicond., 2009, 30(6): 065009. doi: 10.1088/1674-4926/30/6/065009


Advanced Search >>


Wu X F, Liu H X, Su L, Hao Y, Li D, Hu S G. A bootstrapped switch employing a new clock feed-through compensation technique[J]. J. Semicond., 2009, 30(12): 125007. doi: 10.1088/1674-4926/30/12/125007.

Export: BibTex EndNote

Article Metrics

Article views: 2560 Times PDF downloads: 5196 Times Cited by: 0 Times


Manuscript received: 18 August 2015 Manuscript revised: 04 September 2009 Online: Published: 01 December 2009

Email This Article

User name: