Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology

Abstract: Gate-grounded NMOS (GGNMOS) devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-µm silicide CMOS technology. The snapback characteristics of these GGNMOS devices are measured using the transmission line pulsing (TLP) measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-µm silicide CMOS technology are also presented.

Key words: electrostatic discharge,  gate-grounded NMOS,  snapback characteristic,  layout parameters