J. Semicond. > Volume 31 > Issue 10 > Article Number: 105006

A 12-bit current steering DAC with 2-dimensional gradient-error tolerant switching scheme

Chen Hao , Liu Liyuan , Li Dongmei , Zhang Chun and Wang Zhihua

+ Author Affiliations + Find other works by these authors


Abstract: A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18 μm CMOS technology is proposed. It is based on a current steering segmented 6+6 architecture and requires no calibration. By dividing one most significant bit unary source into 16 elements located in 16 separated regions of the array, the linear gradient errors and quadratic errors can be averaged and eliminated effectively. A novel static performance testing method is proposed. The measured differential nonlinearity and integral nonlinearity are 0.42 and 0.39 least significant bit, respectively. For 12-bit resolution, the converter reaches an update rate of 100 MS/s. The chip operates from a single 1.8 V voltage supply, and the core die area is 0.28 mm2.

Key words: current steering DAC


Jianming Lei, Hanshu Gui, Beiwen Hu. A low glitch 12-bit current-steering CMOS DAC for CNC systems. J. Semicond., 2013, 34(2): 025007. doi: 10.1088/1674-4926/34/2/025007


Ning Xu, Fule Li, Chun Zhang, Zhihua Wang. An IP-oriented 11-bit 160 MS/s 2-channel current-steering DAC. J. Semicond., 2014, 35(12): 125011. doi: 10.1088/1674-4926/35/12/125011


Qiu Dong, Fang Sheng, Li Ran, Xie Renzhong, Yi Ting, Hong Zhiliang. A current-steering self-calibration 14-bit 100-MSPs DAC. J. Semicond., 2010, 31(12): 125007. doi: 10.1088/1674-4926/31/12/125007


Yu Jinshan, Fu Dongbing, Li Ruzhang, Yao Yafeng, Yan Gang, Liu Jun, Zhang Ruitao, Yu Zhou, Li Tun. A direct digital frequency synthesizer with high-speed current-steering DAC. J. Semicond., 2009, 30(10): 105006. doi: 10.1088/1674-4926/30/10/105006


Long Cheng, Yu Zhu, Kai Zhu, Chixiao Chen, Junyan Ren. Robust design of a 500-MS/s 10-bit triple-channel current-steering DAC in 40 nm CMOS. J. Semicond., 2013, 34(10): 105007. doi: 10.1088/1674-4926/34/10/105007


Yidie Ye, Yinshui Xia. A current-mode DAC unit circuit with smooth transition. J. Semicond., 2015, 36(7): 075006. doi: 10.1088/1674-4926/36/7/075006


Xueqing Li, Hua Fan, Qi Wei, Zhen Xu, Jianan Liu, Huazhong Yang. A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter. J. Semicond., 2013, 34(8): 085013. doi: 10.1088/1674-4926/34/8/085013


Wang Shaopeng, Ren Yannan, Li Fule, Wang Zhihua. A 400-MS/s 12-bit current-steering D/A converter. J. Semicond., 2012, 33(8): 085006. doi: 10.1088/1674-4926/33/8/085006


Zhu Zhangming, Li Yani, Yang Yintang. An Embedded 1.8V 10bit 120MS/s CMOS Current Steering Digital-to-Analog Converter IP Core. J. Semicond., 2008, 29(3): 588.


Yawei Guo, Li Li, Peng Ou, Zhida Hui, Xu Cheng, Xiaoyang Zeng. A 0.06 mm2 1.0 V 2.5 mW 10 bit 250 MS/s current-steering D/A converter in 65 nm GP CMOS process. J. Semicond., 2014, 35(6): 065002. doi: 10.1088/1674-4926/35/6/065002


Yuan Ling, Ni Weining, Hao Zhikun, Shi Yin, Li Wenchang. A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC. J. Semicond., 2009, 30(9): 095003. doi: 10.1088/1674-4926/30/9/095003


Hualian Tang, Yiqi Zhuang, Xin Jing, Li Zhang. An I/Q DAC with gain matching circuit for a wireless transmitter. J. Semicond., 2013, 34(6): 065006. doi: 10.1088/1674-4926/34/6/065006


Qi Zhao, Ran Li, Dong Qiu, Ting Yi, Yang Liu Bill, Zhiliang Hong. A 14-bit 1-GS/s DAC with a programmable interpolation filter in 65 nm CMOS. J. Semicond., 2013, 34(2): 025004. doi: 10.1088/1674-4926/34/2/025004


Chen Run, Liu Liyuan, Li Dongmei. A Novel Multi-Stage Interpolation Filter Design Technique for High-Resolution Σ-Δ DAC. J. Semicond., 2007, 28(11): 1735.


Yijun Song, Wenyuan Li. A 6-bit 4 GS/s pseudo-thermometer segmented CMOS DAC. J. Semicond., 2014, 35(6): 065007. doi: 10.1088/1674-4926/35/6/065007


Li Dan, Liang Jiayi, Hong Zhiliang, Xu Gang. Integrated Delta-Sigma 1.5bit Power DAC with 100dB Dynamic Range. J. Semicond., 2007, 28(5): 651.


Zhen Xu, Xueqing Li, Jia'nan Liu, Qi Wei, Li Luo, Huazhong Yang. A 14-bit 500-MS/s DAC with digital background calibration. J. Semicond., 2014, 35(3): 035008. doi: 10.1088/1674-4926/35/3/035008


Wang Chunhua, Zhang Qiujing, Liu Haiguang. CMOS current controlled fully balanced current conveyor. J. Semicond., 2009, 30(7): 075009. doi: 10.1088/1674-4926/30/7/075009


Xue Han, Qi Wei, Huazhong Yang, Hui Wang. A single channel, 6-bit 410-MS/s 3bits/stage asynchronous SAR ADC based on resistive DAC. J. Semicond., 2015, 36(5): 055010. doi: 10.1088/1674-4926/36/5/055010


Qiu Dong, Yi Ting, Hong Zhiliang. A low-power triple-mode sigma--delta DAC for reconfigurable (WCDMA/TD-SCDMA/GSM) transmitters. J. Semicond., 2011, 32(2): 025005. doi: 10.1088/1674-4926/32/2/025005


Advanced Search >>


Chen H, Liu L Y, Li D M, Zhang C, Wang Z H. A 12-bit current steering DAC with 2-dimensional gradient-error tolerant switching scheme[J]. J. Semicond., 2010, 31(10): 105006. doi: 10.1088/1674-4926/31/10/105006.

Export: BibTex EndNote

Article Metrics

Article views: 2364 Times PDF downloads: 2718 Times Cited by: 0 Times


Manuscript received: 18 August 2015 Manuscript revised: 20 May 2010 Online: Published: 01 October 2010

Email This Article

User name: