J. Semicond. > Volume 31 > Issue 11 > Article Number: 115007

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

Cai Xiaobo , Li Fule , Zhang Chun and Wang Zhihua

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Abstract: A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter (ADC) in a 0.18 μm complementary metal--oxide semiconductor process is presented. The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements. A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation, respectively. With a 15.5 MHz input signal, the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s. The power consumption is 112 mW at a 1.8 V supply, including output drivers. The chip area is 3.51 mm2, including pads.

Key words: pipelined ADC multi-bit opamp reference

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Cai X B, Li F L, Zhang C, Wang Z H. A 12 bit 100 MS/s pipelined analog to digital converter without calibration[J]. J. Semicond., 2010, 31(11): 115007. doi: 10.1088/1674-4926/31/11/115007.

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History

Manuscript received: 18 August 2015 Manuscript revised: 04 June 2010 Online: Published: 01 November 2010

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