J. Semicond. > Volume 32 > Issue 10 > Article Number: 105011

Design of ternary clocked adiabatic static random access memory

Wang Pengjun and Mei Fengna

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Abstract: Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions.

Key words: multi-valued logic adiabatic ternary SRAM circuit design

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Wang P J, Mei F N. Design of ternary clocked adiabatic static random access memory[J]. J. Semicond., 2011, 32(10): 105011. doi: 10.1088/1674-4926/32/10/105011.

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History

Manuscript received: 20 August 2015 Manuscript revised: 29 May 2011 Online: Published: 01 October 2011

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