J. Semicond. > 2011, Volume 32 > Issue 8 > Article Number: 085005

A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

Yang Jinda , Wang Xianbiao , Li Li , Cheng Xu , Guo Yawei and Zeng Xiaoyang

+ Author Affiliations + Find other works by these authors

PDF

Abstract: A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters (ADCs) has been proposed. In the proposed comparator, a CMOS switch takes the place of the dynamic current sources in the differential comparator, which allows the differential input transistors still to operate in the saturation region at the comparing time. This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage. Additionally, it also features a larger input swing, less sensitivity to common mode voltage, and a simple relationship between the input and reference voltage. This proposed comparator with two traditional comparators has been realized by SMIC 0.13 μm CMOS technology. The contrast experimental results verify these advantages over conventional comparators. It has been used in a 12-bit 100-MS/s pipeline ADC.

Key words: comparator

[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]

Search

Advanced Search >>

GET CITATION

Yang J D, Wang X B, Li L, Cheng X, Guo Y W, Zeng X Y. A novel low-offset dynamic comparator for sub-1-V pipeline ADCs[J]. J. Semicond., 2011, 32(8): 085005. doi: 10.1088/1674-4926/32/8/085005.

Export: BibTex EndNote

Article Metrics

Article views: 2529 Times PDF downloads: 2969 Times Cited by: 0 Times

History

Manuscript received: 18 August 2015 Manuscript revised: 25 March 2011 Online: Published: 01 August 2011

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误