J. Semicond. > Volume 33 > Issue 1 > Article Number: 014005

Impact of parasitic resistance on the ESD robustness of high-voltage devices

Lin Lijuan , Jiang Lingli , Fan Hang and Zhang Bo

+ Author Affiliations + Find other works by these authors

PDF

Abstract: The impacts of substrate parasitic resistance and drain ballast resistance on electrostatic discharge (ESD) robustness of LDMOS are analyzed. By increasing the two parasitic resistances, the ESD robustness of LDMOS are significantly improved. The proposed structures have been successfully verified in a 0.35 μm BCD process without using additional process steps. Experimental results show that the second breakdown current of the optimal structure increases to 3.5 A, which is about 367% of the original device.

Key words: electrostatic dischargehigh-voltage deviceLDMOSparasitic resistance

[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]

Search

Advanced Search >>

GET CITATION

Lin L J, Jiang L L, Fan H, Zhang B. Impact of parasitic resistance on the ESD robustness of high-voltage devices[J]. J. Semicond., 2012, 33(1): 014005. doi: 10.1088/1674-4926/33/1/014005.

Export: BibTex EndNote

Article Metrics

Article views: 2853 Times PDF downloads: 8706 Times Cited by: 0 Times

History

Manuscript received: 20 August 2015 Manuscript revised: 09 August 2011 Online: Published: 01 January 2012

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误