J. Semicond. > Volume 33 > Issue 1 > Article Number: 015004

High performance power-configurable preamplifier in a high-density parallel optical receiver

Wang Xiaoxia and Wang Zhigong

+ Author Affilications + Find other works by these authors

PDF

Abstract: A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb/s high-density ultra-high speed parallel optical communication system. With critical limitations on power consumption, area and fabrication cost, the preamplifier achieves high performance, e.g. high bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate (FCG) stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom consuming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute inductors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature (PVT) variation. Two representative samples provide a trans-impedance gain of 53.9 dBΩ, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBΩ, a 3-dB bandwidth of 8.1 GHz, a power dissipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA/Hz. The chip area is only 0.08 ? 0.08 mm2.

Key words: preamplifierparallel optical receiverlow powerlow costfeed-forward common-gate (simplified FCG) stagepower-configurable

[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[1]

Shimin Feng, Suihua Zhou, Zhiyi Chen. A very low noise preamplifier for extremely low frequency magnetic antenna. J. Semicond., 2013, 34(7): 075003. doi: 10.1088/1674-4926/34/7/075003

[2]

Li Guofeng, Geng Zhiqing, Wu Nanjian. A low power automatic gain control loop for a receiver. J. Semicond., 2010, 31(9): 095009. doi: 10.1088/1674-4926/31/9/095009

[3]

Heping Ma, Hua Xu, Bei Chen, Yin Shi. An ISM 2.4 GHz low power low-IF RF receiver front-end. J. Semicond., 2015, 36(8): 085002. doi: 10.1088/1674-4926/36/8/085002

[4]

Najam Muhammad Amin, Zhigong Wang, Zhiqun Li, Qin Li, Yang Liu. A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology. J. Semicond., 2015, 36(4): 045005. doi: 10.1088/1674-4926/36/4/045005

[5]

Jingjing Chen, Weiyang Liu, Xiaodong Liu, Zhao Zhang, Liyuan Liu, Haiyong Wang, Nanjian Wu. A 2.4 GHz ultra-low power low-IF receiver and MUX-based transmitter for WPAN applications. J. Semicond., 2014, 35(6): 065001. doi: 10.1088/1674-4926/35/6/065001

[6]

Jiao Shilong, Yang Xianming, Zhao Liang, Li Hui, Chen Zhenlong, Chen Tangsheng, Shao Kai, Ye Yutang. A 10Gb/s GaAs PHEMT High Gain Preamplifier for Optical Receivers. J. Semicond., 2007, 28(12): 1902.

[7]

Li Bing, Zhuang Yiqi, Long Qiang, Jin Zhao, Li Zhenrong, Jin Gang. Design of a 0.18μm CMOS multi-band compatible low power GNSS receiver RF frontend. J. Semicond., 2011, 32(3): 035007. doi: 10.1088/1674-4926/32/3/035007

[8]

Jia Hailong, Ren Tong, Lin Min, Chen Fangxiong, Shi Yin, Dai F F. A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver. J. Semicond., 2008, 29(10): 1968.

[9]

Pranav Kumar Asthana, Yogesh Goswami, Bahniman Ghosh. A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel forultra low power applications. J. Semicond., 2016, 37(5): 054002. doi: 10.1088/1674-4926/37/5/054002

[10]

Zhang Feng, Feng Wei, Cui Hao, Yang Yi, Huang Lingyi, Hu Weiwu. A 0.18μm Transmitter and Receiver with High Speed and Low Power. J. Semicond., 2008, 29(5): 836.

[11]

Ma Haifeng, Zhou Feng, Niu Qi, Lü Changhui. Nested Miller Active-Capacitor Frequency Compensation for Low-Power Three-Stage Amplifiers. J. Semicond., 2008, 29(9): 1698.

[12]

Sun Yehui, Jiang Lixin, Qin Shicai. A Low Voltage Low Power CMOS 5Gb/s Transceiver. J. Semicond., 2007, 28(8): 1283.

[13]

Chenjian Wu, Zhiqun Li, Ge Sun. A low voltage low power up-conversion mixer for WSN application. J. Semicond., 2014, 35(4): 045006. doi: 10.1088/1674-4926/35/4/045006

[14]

Ying Jianhua, Chen Jia, Wang Jie. Design of Low Power,High PSRR Voltage Reference. J. Semicond., 2007, 28(6): 975.

[15]

Weiyang Liu, Jingjing Chen, Haiyong Wang, Nanjian Wu. A low power 2.4 GHz transceiver for ZigBee applications. J. Semicond., 2013, 34(8): 085007. doi: 10.1088/1674-4926/34/8/085007

[16]

Yu Yang, Zhao Qian, Shao Zhibiao. A Low Power SRAM/SOI Memory Cell Design. J. Semicond., 2006, 27(2): 318.

[17]

Quan Zhou, Shuxu Guo, Jingyi Song, Zhaohan Li, Guotong Du, Yuchun Chang. A low power discrete operation mode for punchthrough phototransistor. J. Semicond., 2013, 34(7): 074010. doi: 10.1088/1674-4926/34/7/074010

[18]

Chengying Chen, Hainan Liu, Yong Hei, Jun Fan, Xiaoyu Hu. A low-power high-performance configurable auto-gain control loop for a digital hearing aid SoC. J. Semicond., 2013, 34(10): 105011. doi: 10.1088/1674-4926/34/10/105011

[19]

Wei Benfu, Yuan Guoshun. Design of a Low Noise,Low Power Audio Power Amplifierfor Driving Headphones. J. Semicond., 2006, 27(S1): 29.

[20]

Tong Xingyuan, Zhu Zhangming, Yang Yintang. An offset cancellation technique in a switched-capacitor comparator for SAR ADCs. J. Semicond., 2012, 33(1): 015011. doi: 10.1088/1674-4926/33/1/015011

Search

Advanced Search >>

GET CITATION

Wang X X, Wang Z G. High performance power-configurable preamplifier in a high-density parallel optical receiver[J]. J. Semicond., 2012, 33(1): 015004. doi: 10.1088/1674-4926/33/1/015004.

Export: BibTex EndNote

Article Metrics

Article views: 1995 Times PDF downloads: 1622 Times Cited by: 0 Times

History

Manuscript received: 03 December 2014 Manuscript revised: 19 August 2011 Online: Published: 01 January 2012

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误