J. Semicond. > Volume 33 > Issue 1 > Article Number: 015011

An offset cancellation technique in a switched-capacitor comparator for SAR ADCs

Tong Xingyuan , Zhu Zhangming and Yang Yintang

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Abstract: An offset cancellation technique for a SAR (successive approximation register) ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18 μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to < 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.

Key words: A/D converterswitched-capacitor comparatorpreamplifierregenerative latchlow powerlow offset


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Tong X Y, Zhu Z M, Yang Y T. An offset cancellation technique in a switched-capacitor comparator for SAR ADCs[J]. J. Semicond., 2012, 33(1): 015011. doi: 10.1088/1674-4926/33/1/015011.

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Manuscript received: 20 August 2015 Manuscript revised: 08 October 2011 Online: Published: 01 January 2012

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