J. Semicond. > Volume 33 > Issue 11 > Article Number: 115004

Pulse swallowing frequency divider with low power and compact structure

Gao Haijun , Sun Lingling , Cai Chaobo and Zhan Haiting

+ Author Affilications + Find other works by these authors


Abstract: A pulse swallowing frequency divider with low power and compact structure is presented. One of the DFFs in the divided by 2/3 prescaler is controlled by the modulus control signal, and automatically powered off when it has no contribution to the operation of the prescaler. The DFFs in the program counter and the swallow counter are shared to compose a compact structure, which reduces the power consumption further. The proposed multi-modulus frequency divider was implemented in a standard 65 nm CMOS process with an area of 28 × 22 μm2. The power consumption of the divider is 0.6 mW under 1.2 V supply voltage when operating at 988 MHz.

Key words: frequency dividerlow powerprescalermulti-modulus


Li Zhiqiang, Chen Liqiang, Zhang Jian, Zhang Haiying. A Programmable 2.4GHz CMOS Multi-Modulus Frequency Divider. J. Semicond., 2008, 29(2): 224.


Lei Xuemei, Wang Zhigong, Wang Keping, Li Wei. A novel wideband low phase noise 2 : 1 frequency divider. J. Semicond., 2010, 31(6): 065005. doi: 10.1088/1674-4926/31/6/065005


Yuan Quan, Yang Haigang, Dong Fangyuan, Zhong Lungui. A "Time Reuse" Technique for Design of a Low-Power,High-Speed Multi-Modulus Divider in a Frequency Synthesizer. J. Semicond., 2008, 29(4): 794.


Najam Muhammad Amin, Zhigong Wang, Zhiqun Li, Qin Li, Yang Liu. A low power, low noise figure quadrature demodulator for a 60 GHz receiver in 65-nm CMOS technology. J. Semicond., 2015, 36(4): 045005. doi: 10.1088/1674-4926/36/4/045005


Chen Zuotian, Wu Xuan, Tang Shoulong, Wu Jianhui. CMOS Implementation of a Wideband Low Phase Noise PLL Frequency Synthesizer. J. Semicond., 2006, 27(10): 1838.


Du Rui, Dai Yang, Yang Fuhua. Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode. J. Semicond., 2008, 29(7): 1292.


Shu Haiyong, Li Zhiqun. A 5-GHz programmable frequency divider in 0.18-μm CMOS technology. J. Semicond., 2010, 31(5): 055004. doi: 10.1088/1674-4926/31/5/055004


Geng Zhiqing, Yan Xiaozhou, Lou Wenfeng, Feng Peng, Wu Nanjian. A low power fast-settling frequency-presetting PLL frequency synthesizer. J. Semicond., 2010, 31(8): 085002. doi: 10.1088/1674-4926/31/8/085002


Jia Hailong, Ren Tong, Lin Min, Chen Fangxiong, Shi Yin, Dai F F. A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver. J. Semicond., 2008, 29(10): 1968.


Li Bing, Zhuang Yiqi, Long Qiang, Jin Zhao, Li Zhenrong, Jin Gang. Design of a 0.18μm CMOS multi-band compatible low power GNSS receiver RF frontend. J. Semicond., 2011, 32(3): 035007. doi: 10.1088/1674-4926/32/3/035007


Hui Hong, Shiliang Li, Tao Zhou. Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications. J. Semicond., 2015, 36(4): 045009. doi: 10.1088/1674-4926/36/4/045009


Ma Haifeng, Zhou Feng, Niu Qi, Lü Changhui. Nested Miller Active-Capacitor Frequency Compensation for Low-Power Three-Stage Amplifiers. J. Semicond., 2008, 29(9): 1698.


Nan Chen, Shengxi Diao, Lu Huang, Xuefei Bai, Fujiang Lin. Design optimizations of phase noise, power consumption and frequency tuning for VCO. J. Semicond., 2013, 34(9): 095009. doi: 10.1088/1674-4926/34/9/095009


Yu Yunfeng, Yue Jianlian, Xiao Shimao, Zhuang Haixiao, Ma Chengyan, Ye Tianchun. A low-power CMOS frequency synthesizer for GPS receivers. J. Semicond., 2010, 31(6): 065012. doi: 10.1088/1674-4926/31/6/065012


Xiaobao Yu, Siyang Han, Zongming Jin, Zhihua Wang, Baoyong Chi. A class-C VCO based Σ-Δ fraction-N frequency synthesizer with AFC for 802.11ah applications. J. Semicond., 2015, 36(9): 095003. doi: 10.1088/1674-4926/36/9/095003


Sun Yehui, Jiang Lixin, Qin Shicai. A Low Voltage Low Power CMOS 5Gb/s Transceiver. J. Semicond., 2007, 28(8): 1283.


Chenjian Wu, Zhiqun Li, Ge Sun. A low voltage low power up-conversion mixer for WSN application. J. Semicond., 2014, 35(4): 045006. doi: 10.1088/1674-4926/35/4/045006


Lei Xuemei, Wang Zhigong, Wang Keping. A wideband low power low phase noise dual-modulus prescaler. J. Semicond., 2011, 32(2): 025011. doi: 10.1088/1674-4926/32/2/025011


Ying Jianhua, Chen Jia, Wang Jie. Design of Low Power,High PSRR Voltage Reference. J. Semicond., 2007, 28(6): 975.


Weiyang Liu, Jingjing Chen, Haiyong Wang, Nanjian Wu. A low power 2.4 GHz transceiver for ZigBee applications. J. Semicond., 2013, 34(8): 085007. doi: 10.1088/1674-4926/34/8/085007


Advanced Search >>


Gao H J, Sun L L, Cai C B, Zhan H T. Pulse swallowing frequency divider with low power and compact structure[J]. J. Semicond., 2012, 33(11): 115004. doi: 10.1088/1674-4926/33/11/115004.

Export: BibTex EndNote

Article Metrics

Article views: 1301 Times PDF downloads: 4870 Times Cited by: 0 Times


Manuscript received: 20 August 2015 Manuscript revised: 17 May 2012 Online: Published: 01 November 2012

Email This Article

User name: