J. Semicond. > Volume 34 > Issue 2 > Article Number: 025012

A low jitter PLL clock used for phase change memory

Xiao Hong , , Houpeng Chen , Zhitang Song , Daolin Cai and Xi Li

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Abstract: A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.

Key words: PLLPFDcharge pumpVCOPCM

Abstract: A fully integrated low-jitter, precise frequency CMOS phase-locked loop (PLL) clock for the phase change memory (PCM) drive circuit is presented. The design consists of a dynamic dual-reset phase frequency detector (PFD) with high frequency acquisition, a novel low jitter charge pump, a CMOS ring oscillator based voltage-controlled oscillator (VCO), a 2nd order passive loop filter, and a digital frequency divider. The design is fabricated in 0.35 μm CMOS technology and consumes 20 mW from a supply voltage of 5 V. In terms of the PCM's program operation requirement, the output frequency range is from 1 to 140 MHz. For the 140 MHz output frequency, the circuit features a cycle-to-cycle jitter of 28 ps RMS and 250 ps peak-to-peak.

Key words: PLLPFDcharge pumpVCOPCM



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Lai S, Lowrey T. OUM——a 180 nm nonvolatile memory cell element technology for stand alone and embedded applications[J]. IEDM, 2001, 36(5): 1.

[2]

Lavizzari S, Sharma D, Ielmini D. Threshold-switching delay controlled by 1/f current fluctuations in phase-change memory devices[J]. IEEE Trans Electron Devices, 2010, 57(5): 1047. doi: 10.1109/TED.2010.2042768

[3]

Shi X T, Imfeld K. A low-jitter and low-power CMOS PLL for clock multiplication[J]. Proceedings of the 32nd European IEEE Solid-State Circuits Conference, ESSCIRC, 2006: 174.

[4]

Keliu S. CMOS PLL synthesizers analysis and design[J]. Boston, Springer Science + Business Media, 2005.

[5]

Todd C W, Beomsup K. Analysis of timing jitter in CMOS ring oscillators[J]. IEEE Proceedings of ISCAS, 1994: 191.

[6]

Mansuri M, Liu D, Yang C K. Fast frequency acquisition phase-frequency detectors for GSamples/s phase-locked loops[J]. IEEE J Solid-State Circuits, 2002, 37(10): 1331. doi: 10.1109/JSSC.2002.803048

[7]

Jae-Shin L, Min-Sun K. Charge pump with perfect current matching characteristics in phase-locked loops[J]. Electron Lett, 2000, 36(23): 1907. doi: 10.1049/el:20001358

[8]

Mansuri M, Yang C K. A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation[J]. IEEE J Solid-State Circuits, 2003, 38(11): 1804. doi: 10.1109/JSSC.2003.818300

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John G M, Mark A H. Precise delay generation using coupled oscillators[J]. IEEE J Solid-State Circuits, 1993, 28(12): 1273. doi: 10.1109/4.262000

[10]

Hong X, Chen H P, Song Z T. A low noise clock generator for phase change memories[J]. Microelectron, 2011, 41(4): 540.

[11]

Ge Y, Jia S. A fast acquisition PLL with wide tuning range[J]. Chinese Journal of Semiconductors, 2007, 28(3): 365.

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X Hong, H P Chen, Z T Song, D L Cai, X Li. A low jitter PLL clock used for phase change memory[J]. J. Semicond., 2013, 34(2): 025012. doi: 10.1088/1674-4926/34/2/025012.

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History

Manuscript received: 16 July 2012 Manuscript revised: 28 September 2012 Online: Published: 01 February 2013

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