J. Semicond. > Volume 34 > Issue 8 > Article Number: 084005

A vertically integrated capacitorless memory cell

Xiaodong Tong , , Hao Wu , Lichuan Zhao , Ming Wang and Huicai Zhong

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Abstract: A two-port capacitorless PNPN device with high density, high speed and low power memory fabricated using standard CMOS technology is presented. Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed (ns level), large read current margin (read current ratio of 104×), low process variation, good thermal reliability and available retention time (190 ms). Furthermore, the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.

Key words: PNPN diodetwo-portcross-point

Abstract: A two-port capacitorless PNPN device with high density, high speed and low power memory fabricated using standard CMOS technology is presented. Experiments and calibrated simulations were conducted which prove that this new memory cell has a high operation speed (ns level), large read current margin (read current ratio of 104×), low process variation, good thermal reliability and available retention time (190 ms). Furthermore, the new memory cell is free of the cyclic endurance/reliability problems induced by hot-carrier injection due to the gateless structure.

Key words: PNPN diodetwo-portcross-point



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[2]

Cho H J, Nemati F, Roy R. A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT)[J]. IEEE International Electron Devices Meeting (IEDM), 2005.

[3]

Han J W, Choi Y K. Bistable resistor (biristor)-gateless silicon nanowire memory[J]. Symposium on VLSI Technology, 2010: 171.

[4]

Gibbons J F. A critique of the theory of p-n-p-n devices[J]. IEEE Trans Electron Devices, 1964, 11(9): 406. doi: 10.1109/T-ED.1964.15352

[5]

Kau D C, Tang S, Karpov I V. A stackable cross point phase change memory[J]. IEEE International Electron Devices Meeting (IEDM), 2009.

[6]

Tong X, Wu H, Liang Q. On the design of 2-port SRAM memory cells using PNPN diodes for VLSI application[J]. IEEE International Conference on Simulation of Semiconductor Processes and devices (SISPAD), Denver, CO, USA, 2012.

[7]

Liang J, Jeyasingh R G D, Chen H Y. An ultra-low reset current cross-point phase change memory with carbon nanotube electrodes[J]. IEEE Trans Electron Devices, 2012, 59(4): 1155. doi: 10.1109/TED.2012.2184542

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X D Tong, H Wu, L C Zhao, M Wang, H C Zhong. A vertically integrated capacitorless memory cell[J]. J. Semicond., 2013, 34(8): 084005. doi: 10.1088/1674-4926/34/8/084005.

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History

Manuscript received: 29 January 2013 Manuscript revised: 19 February 2013 Online: Published: 01 August 2013

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