J. Semicond. > Volume 35 > Issue 1 > Article Number: 015009

A low-leakage and NBTI-mitigated N-type domino logic

Huaguo Liang 1, , Hui Xu 2, 3, , , Zhengfeng Huang 1, and Maoxiang Yi 1,

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Abstract: NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDD, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.

Key words: domino logic circuitnegative bias temperature instabilityleakage currentstandby mode

Abstract: NBTI-induced transistor aging has become a prominent factor affecting the reliability of circuits. Reducing leakage consumption is one of the major design goals. Domino logic circuits are applied extensively in high-performance integrated circuits. A circuit technique for mitigating NBTI-induced degradation and reduce standby leakage current is presented in this paper. Two transistors are added to the standard domino circuit to pull both the dynamic node and the output up to VDD, which puts both the keeper and the inverter pMOS transistor into recovery mode in standby mode. Due to the stack effect, leakage current is reduced by the all-0 input vector and the added transistors. Experimental results reveal up to 33% NBTI-induced degradation reduction and up to 79% leakage current reduction.

Key words: domino logic circuitnegative bias temperature instabilityleakage currentstandby mode



References:

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Feng Chaochao, Chen Xun, Yi Xiaofei. An improved high fan-in Domino circuit for high performance microprocessors[J]. Journal of Semiconductors, 2008, 29(9): 1740.

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Wang Jinhui, Gong Na, Hou Ligang. Charge self-compensation technology research for low power and high performance Domino circuits[J]. Journal of Semiconductors, 2008, 29(7): 1412.

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Wang J, Wu W, Lei Z. Power and delay estimation for dynamic OR gates with header and footer transistor based on wavelet neural networks[J]. 10th International Conference on Ultimate Integration of Silicon, 2009: 241.

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Hua C H, Hwang W, Chen C K. Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits[J]. IEEE International Symposium on Circuits and Systems, 2005: 444.

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Bhardwaj S, Wenping W, Vattikonda R. Predictive modeling of the NBTI effect for reliable design[J]. Proc Custom Integrated Circuits Conference, 2006: 189.

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Paul B C, Kunhyuk K, Kufluoglu H. Temporal performance degradation under NBTI:estimation and design for improved reliability of nanoscale circuits[J]. Proc Design, Automation and Test in Europe, 2006: 780.

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Gong N, Tang G, Wang J. Novel adaptive keeper LBL technique for low power and high performance register files[J]. IEEE International SOC Conference (SOCC), 2011: 30.

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Eriksson H, Larsson-Edefors P, Henriksson T. Full-custom vs. standard-cell design flow:an adder case study[J]. Proceedings of the Asia and South Pacific Design Automation Conference, Kitakyushu, Japan, 2003: 507.

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Eleyan N N, Ken L, Kamal M. Semi-custom design flow:leveraging place and route tools in custom circuit design[J]. IEEE International Conference on IC Design and Technology, 2009: 143.

[29]

Lin I C, Lin C H, Li K H. Leakage and aging optimization using transmission gate-based technique[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(1): 87. doi: 10.1109/TCAD.2012.2214478

[30]

Abdollahi A, Fallah F, Pedram M. Leakage current reduction in CMOS VLSI circuits by input vector control[J]. IEEE Trans Very Large Scale Integration (VLSI) Syst, 2004, 12(2): 140. doi: 10.1109/TVLSI.2003.821546

[31]

Khandelwal V, Srivastava A. Leakage control through fine-grained placement and sizing of sleep transistors[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(7): 1246. doi: 10.1109/TCAD.2006.888282

[1]

Kursun V, Friedman E G. Sleep switch dual threshold voltage domino logic with reduced standby leakage current[J]. IEEE Trans Very Large Scale Integration (VLSI) Syst, 2004, 12(5): 485. doi: 10.1109/TVLSI.2004.826198

[2]

Hyungwoo L, Heejung S, Seungho J. Statistical leakage estimation for DRAM circuits[J]. Proc 2nd Asia Symposium on Quality Electronic Design (ASQED), 2010: 243.

[3]

Hui X, Huaguo L, Zhengfeng H. An aging tolerant Domino gate[J]. J Circuits Syst, 2012, 17(5): 91.

[4]

Kaffashian M H, Lotfi R, Mafinezhad K. Impact of NBTI on performance of domino logic circuits in nano-scale CMOS[J]. Microelectron J, 2011(32): 1327.

[5]

Kaffashian M H, Lotfi R, Mafinezhadand K. An optimization method for NBTI-aware design of Domino logic circuits in nano-scale CMOS[J]. Electron Express, 2011, 81: 406.

[6]

Yu W, Hong L, Ku H. Temperature-aware NBTI modeling and the impact of input vector control on performance degradation[J]. Proc Design, Automation & Test in Europe Conference & Exhibition, 2007: 1.

[7]

Feng Chaochao, Chen Xun, Yi Xiaofei. An improved high fan-in Domino circuit for high performance microprocessors[J]. Journal of Semiconductors, 2008, 29(9): 1740.

[8]

Wang Jinhui, Gong Na, Hou Ligang. Charge self-compensation technology research for low power and high performance Domino circuits[J]. Journal of Semiconductors, 2008, 29(7): 1412.

[9]

Borkar S. Circuit techniques for subthreshold leakage avoidance, control and tolerance[J]. IEDM Technical Digest, IEEE International Electron Devices Meeting, 2004: 421.

[10]

Anis M H, Allam M W, Elmasry M I. Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies[J]. IEEE Trans Very Large Scale Integration Syst, 2002, 10(2): 71. doi: 10.1109/92.994977

[11]

Song J, Yinhe H, Huawei L. On predicting circuit aging via considering actual workload[J]. Journal of Computer-Aided Design & Computer Graphics, 2010(12): 2242.

[12]

Wu K C, Marculescu D. Joint logic restructuring and pin reordering against NBTI-induced performance degradation[J]. Proc Design, Automation & Test in Europe Conference & Exhibition, 2009: 75.

[13]

Wang J, Wu W, Lei Z. Power and delay estimation for dynamic OR gates with header and footer transistor based on wavelet neural networks[J]. 10th International Conference on Ultimate Integration of Silicon, 2009: 241.

[14]

Hua C H, Hwang W, Chen C K. Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits[J]. IEEE International Symposium on Circuits and Systems, 2005: 444.

[15]

Bhardwaj S, Wenping W, Vattikonda R. Predictive modeling of the NBTI effect for reliable design[J]. Proc Custom Integrated Circuits Conference, 2006: 189.

[16]

Wang W, Wei Z, Yang S. An efficient method to identify critical gates under circuit aging[J]. IEEE/ACM International Conference on Computer-Aided Design, 2007: 735.

[17]

Wu K C, Marculescu D. Aging-aware timing analysis and optimization considering path sensitization[J]. Proc Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, 2011: 1.

[18]

Predictive technology model (PTM). http://www.eas.asu.edu/ptm/

[19]

Wang Y, Chen X, Wang W. Leakage power and circuit aging cooptimization by gate replacement techniques[J]. IEEE Trans Very Large Scale Integration Syst, 2011, 19(4): 615. doi: 10.1109/TVLSI.2009.2037637

[20]

Siddiqua T, Gurumurthi S. Recovery boosting:a technique to enhance NBTI recovery in SRAM arrays[J]. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2010: 393.

[21]

Vattikonda R, Wang W, Yu C. Modeling and minimization of PMOS NBTI effect for robust nanometer design[J]. 43rd ACM/IEEE Design Automation Conference, 2006: 1047.

[22]

Wang Y, Chen X, Wang W. On the efficacy of input Vector control to mitigate NBTI effects and leakage power[J]. International Symposium on Quality of Electronic Design, ISQED, 2009: 19.

[23]

Bild D R, Bok G E, Dick R P. Minimization of NBTI performance degradation using internal node control[J]. Proc Design, Automation & Test in Europe Conference & Exhibition, 2009: 148.

[24]

Lin Y, Gang Q. A combined gate replacement and input vector control approach for leakage current reduction[J]. IEEE Trans Very Large Scale Integration (VLSI) Syst, 2006, 14(2): 173. doi: 10.1109/TVLSI.2005.863747

[25]

Paul B C, Kunhyuk K, Kufluoglu H. Temporal performance degradation under NBTI:estimation and design for improved reliability of nanoscale circuits[J]. Proc Design, Automation and Test in Europe, 2006: 780.

[26]

Gong N, Tang G, Wang J. Novel adaptive keeper LBL technique for low power and high performance register files[J]. IEEE International SOC Conference (SOCC), 2011: 30.

[27]

Eriksson H, Larsson-Edefors P, Henriksson T. Full-custom vs. standard-cell design flow:an adder case study[J]. Proceedings of the Asia and South Pacific Design Automation Conference, Kitakyushu, Japan, 2003: 507.

[28]

Eleyan N N, Ken L, Kamal M. Semi-custom design flow:leveraging place and route tools in custom circuit design[J]. IEEE International Conference on IC Design and Technology, 2009: 143.

[29]

Lin I C, Lin C H, Li K H. Leakage and aging optimization using transmission gate-based technique[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(1): 87. doi: 10.1109/TCAD.2012.2214478

[30]

Abdollahi A, Fallah F, Pedram M. Leakage current reduction in CMOS VLSI circuits by input vector control[J]. IEEE Trans Very Large Scale Integration (VLSI) Syst, 2004, 12(2): 140. doi: 10.1109/TVLSI.2003.821546

[31]

Khandelwal V, Srivastava A. Leakage control through fine-grained placement and sizing of sleep transistors[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2007, 26(7): 1246. doi: 10.1109/TCAD.2006.888282

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H G Liang, H Xu, Z F Huang, M X Yi. A low-leakage and NBTI-mitigated N-type domino logic[J]. J. Semicond., 2014, 35(1): 015009. doi: 10.1088/1674-4926/35/1/015009.

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Manuscript received: 22 May 2013 Manuscript revised: 24 July 2013 Online: Published: 01 January 2014

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