J. Semicond. > Volume 35 > Issue 2 > Article Number: 025003

A 130 nm CMOS low-power SAR ADC for wide-band communication systems

Chenghao Bian 1, 2, , , Jun Yan 1, , Yin Shi 1, and Ling Sun 2,

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Abstract: This paper presents a low power 9-bit 80 MS/s SAR ADC that uses the comparator-sharing technique in a 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The 'set-and-down' switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.

Key words: ADCSARcapacitor-sharingerror compensationcapacitor arraydynamic logic

Abstract: This paper presents a low power 9-bit 80 MS/s SAR ADC that uses the comparator-sharing technique in a 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The 'set-and-down' switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.

Key words: ADCSARcapacitor-sharingerror compensationcapacitor arraydynamic logic



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Harpe P, Cntatore E, Roermund A V. A 2.2/2.7 fJ/conversion-step 10/1240 kS/s SAR ADC with data-driven noise reduction[J]. International Solid-State Circuits Conference, 2013: 270.

[2]

Ma Jun, Guo Yawei, Wu Yue. A 1-V 10-bit 80-MS/s 1.6-mW SAR ADC in 65-nm GP CMOS[J]. Journal of Semiconductors, 2013, 34(8): 085014. doi: 10.1088/1674-4926/34/8/085014

[3]

Kuttner F. A 1.2 V 10 b 20 MSample/s non-binary successive approximation ADC in 0.13 μm CMOS[J]. International Solid-State Circuits Conference, 2002: 176.

[4]

Cho S H, Lee C K, Kwon J K. A 550-μ W 10-b 40-MS/s SAR ADC with multistep addition-only digital error correction[J]. IEEE J Solid-State Circuits, 2011, 46(8): 1881. doi: 10.1109/JSSC.2011.2151450

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Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731. doi: 10.1109/JSSC.2010.2042254

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Yoshioka M, Ishikawa K, Takayama T. A 10 b 50 MS/s 820 μW SAR ADC with on-chip digital calibration[J]. International Solid-State Circuits Conference, 2010: 384.

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Zhu Y, Chan C H, Chio U F. A 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. International Solid-State Circuits Conference, 2010: 1111.

[8]

Tsai J H, Chen Y J, Shen M H. A 1-V, 8 b, 40 MS/s, 113 μW charge-recycling SAR ADC with a 14 μW asynchronous controller[J]. IEEE Symp on VLSI Circuit, 2011: 264.

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C H Bian, J Yan, Y Shi, L Sun. A 130 nm CMOS low-power SAR ADC for wide-band communication systems[J]. J. Semicond., 2014, 35(2): 025003. doi: 10.1088/1674-4926/35/2/025003.

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History

Manuscript received: 09 July 2013 Manuscript revised: 13 September 2013 Online: Published: 01 February 2014

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