J. Semicond. > Volume 35 > Issue 5 > Article Number: 055006

A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS

Wei Lü 1, , Duona Luo 1, , Fengcheng Mei 1, , Jiaqi Yang 1, , Libin Yao 2, , Lin He 1, , and Fujiang Lin 1,

+ Author Affilications + Find other works by these authors

PDF

Abstract: This paper presents a 0.6 V 10 bit successive approximation register (SAR) ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120×300 μm2.

Key words: SAR ADCmonotonic switchingcommon mode stabilizercomparator offset

Abstract: This paper presents a 0.6 V 10 bit successive approximation register (SAR) ADC design dedicated to the wireless sensor network application. It adopts a monotonic switching scheme in the DAC to save chip area and power consumption. The main drawback of the monotonic switching scheme is its large common mode shift and the associated comparator offset variation. Due to the limited headroom at the 0.6 V supply voltage, the conventional constant current biasing technique cannot be applied to the dynamic comparator. In this design, a common mode stabilizer is introduced to address this issue in low-voltage design. The effectiveness of this method is verified through both simulation and measurement results. Fabricated with 1P8M 0.13 μm CMOS technology, the proposed SAR ADC consumes 6.3 μW at 1 MS/s from a 0.6 V supply, and achieves 51.25 dB SNDR at the Nyquist frequency and FOM of 21 fJ/conversion-step. The core area is only 120×300 μm2.

Key words: SAR ADCmonotonic switchingcommon mode stabilizercomparator offset



References:

[1]

Rajput S S, Jamuar S S. Low voltage analog circuit design techniques[J]. IEEE Circuits Syst Mag, 2002, 2(1): 24. doi: 10.1109/MCAS.2002.999703

[2]

Verma N, Chandrakasan A P. An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes[J]. IEEE J Solid-State Circuits, 2007, 42(6): 1196. doi: 10.1109/JSSC.2007.897157

[3]

Yip M, Chandrakasan A P. A resolution-reconfigurable 5-to-10-bit 0.4-to-1 V power scalable SAR ADC for sensor applications[J]. IEEE J Solid-State Circuits, 2013, 48(6): 1453. doi: 10.1109/JSSC.2013.2254551

[4]

Harpe P, Dolmans G, Philips K. A 0.7 V 7-to-10 bit 0-to-2 MS/s flexible SAR ADC for ultra low-power wireless sensor nodes[J]. IEEE European Solid-State Circuits Conference (ESSCIRC), 2012: 373.

[5]

Shikata A, Sekimoto R, Kuroda T. A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS[J]. IEEE J Solid-State Circuits, 2012, 47(4): 1022. doi: 10.1109/JSSC.2012.2185352

[6]

Lee S K, Park S J, Park H J. A 1.3μW 0.6 V 8.7-ENOB successive approximation ADC in a 0.18μm CMOS[J]. Symposium on VLSI Circuits Digest of Technical Papers, 2009: 242.

[7]

Lin G Y, Huang H Y, Hsieh C C. A 0.05 mm2 0.6 V 500 kS/s 14.3 fJ/Conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager[J]. IEEE Asian Solid-State Circuits Conference (ASSCC), 2012: 165.

[8]

Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731. doi: 10.1109/JSSC.2010.2042254

[9]

Zhu Y, Chan C H, Chio U F. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE J Solid-State Circuits, 2010, 45(5): 1111.

[10]

Ginsburg B P, Chandrakasan A P. An energy-efficient charge recycling approach for a SAR converter with capacitive DAC[J]. IEEE Int Symp Circuits and Systems (ISCAS), 2005: 184.

[11]

Liu C C, Chang S J, Huang G Y. A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process[J]. Symposium on VLSI Circuits Digest of Technical Papers, 2009: 236.

[12]

Razavi B. Design of analog CMOS integrated circuits. New York: McGraw-Hill, Inc, 2000

[13]

Schinkel D, Mensink E, Klumperink E. A double-tail latch-type voltage sense amplifier with 18 ps Setup+Hold time[J]. IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2007: 314.

[14]

Chen S M, Brodersen R W. A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS[J]. IEEE J Solid-State Circuits, 2006, 41(12): 2669. doi: 10.1109/JSSC.2006.884231

[15]

Promitzer G. 12-bit low-power fully differential noncalibrating successive approximation ADC with 1 MS/s[J]. IEEE J Solid-State Circuits, 2001, 36(7): 1138. doi: 10.1109/4.933473

[16]

Agnes A, Bonizzoni E, Malcovati P. A 9.4-ENOB 1 V 3.8μW 100 kS/s SAR ADC with time-domain comparator[J]. IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2008: 246.

[1]

Rajput S S, Jamuar S S. Low voltage analog circuit design techniques[J]. IEEE Circuits Syst Mag, 2002, 2(1): 24. doi: 10.1109/MCAS.2002.999703

[2]

Verma N, Chandrakasan A P. An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes[J]. IEEE J Solid-State Circuits, 2007, 42(6): 1196. doi: 10.1109/JSSC.2007.897157

[3]

Yip M, Chandrakasan A P. A resolution-reconfigurable 5-to-10-bit 0.4-to-1 V power scalable SAR ADC for sensor applications[J]. IEEE J Solid-State Circuits, 2013, 48(6): 1453. doi: 10.1109/JSSC.2013.2254551

[4]

Harpe P, Dolmans G, Philips K. A 0.7 V 7-to-10 bit 0-to-2 MS/s flexible SAR ADC for ultra low-power wireless sensor nodes[J]. IEEE European Solid-State Circuits Conference (ESSCIRC), 2012: 373.

[5]

Shikata A, Sekimoto R, Kuroda T. A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS[J]. IEEE J Solid-State Circuits, 2012, 47(4): 1022. doi: 10.1109/JSSC.2012.2185352

[6]

Lee S K, Park S J, Park H J. A 1.3μW 0.6 V 8.7-ENOB successive approximation ADC in a 0.18μm CMOS[J]. Symposium on VLSI Circuits Digest of Technical Papers, 2009: 242.

[7]

Lin G Y, Huang H Y, Hsieh C C. A 0.05 mm2 0.6 V 500 kS/s 14.3 fJ/Conversion-step 11-bit two-step switching SAR ADC for 3-dimensional stacking CMOS imager[J]. IEEE Asian Solid-State Circuits Conference (ASSCC), 2012: 165.

[8]

Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731. doi: 10.1109/JSSC.2010.2042254

[9]

Zhu Y, Chan C H, Chio U F. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE J Solid-State Circuits, 2010, 45(5): 1111.

[10]

Ginsburg B P, Chandrakasan A P. An energy-efficient charge recycling approach for a SAR converter with capacitive DAC[J]. IEEE Int Symp Circuits and Systems (ISCAS), 2005: 184.

[11]

Liu C C, Chang S J, Huang G Y. A 0.92 mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process[J]. Symposium on VLSI Circuits Digest of Technical Papers, 2009: 236.

[12]

Razavi B. Design of analog CMOS integrated circuits. New York: McGraw-Hill, Inc, 2000

[13]

Schinkel D, Mensink E, Klumperink E. A double-tail latch-type voltage sense amplifier with 18 ps Setup+Hold time[J]. IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2007: 314.

[14]

Chen S M, Brodersen R W. A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS[J]. IEEE J Solid-State Circuits, 2006, 41(12): 2669. doi: 10.1109/JSSC.2006.884231

[15]

Promitzer G. 12-bit low-power fully differential noncalibrating successive approximation ADC with 1 MS/s[J]. IEEE J Solid-State Circuits, 2001, 36(7): 1138. doi: 10.1109/4.933473

[16]

Agnes A, Bonizzoni E, Malcovati P. A 9.4-ENOB 1 V 3.8μW 100 kS/s SAR ADC with time-domain comparator[J]. IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2008: 246.

[1]

Xiaofei Wang, Hong Zhang, Jie Zhang, Xin Du, Yue Hao. A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background. J. Semicond., 2016, 37(3): 035002. doi: 10.1088/1674-4926/37/3/035002

[2]

Dong Li, Qiao Meng, Fei Li. A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS. J. Semicond., 2016, 37(1): 015004. doi: 10.1088/1674-4926/37/1/015004

[3]

Jixuan Xiang, Chixiao Chen, Fan Ye, Jun Xu, Ning Li, Junyan Ren. A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators. J. Semicond., 2015, 36(5): 055009. doi: 10.1088/1674-4926/36/5/055009

[4]

Jihai Duan, Zhiyong Zhu, Jinli Deng, Weilin Xu. An 8 bit 1 MS/s SAR ADC with 7.72-ENOB. J. Semicond., 2017, 38(8): 085005. doi: 10.1088/1674-4926/38/8/085005

[5]

Beichen Zhang, Bingbing Yao, Liyuan Liu, Jian Liu, Nanjian Wu. High power-efficient asynchronous SAR ADC for IoT devices. J. Semicond., 2017, 38(10): 105001. doi: 10.1088/1674-4926/38/10/105001

[6]

Jingjing Wang, Zemin Feng, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren. A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array. J. Semicond., 2016, 37(5): 055003. doi: 10.1088/1674-4926/37/5/055003

[7]

Yuxiao Lu, Lu Sun, Zhe Li, Jianjun Zhou. A single-channel 10-bit 160 MS/s SAR ADC in 65 nm CMOS. J. Semicond., 2014, 35(4): 045009. doi: 10.1088/1674-4926/35/4/045009

[8]

Yan Song, Zhongming Xue, Pengcheng Yan, Jueying Zhang, Li Geng. A 0.6-V 8.3-ENOB asynchronous SAR ADC for biomedical applications. J. Semicond., 2014, 35(8): 085007. doi: 10.1088/1674-4926/35/8/085007

[9]

Hui Hong, Shiliang Li, Tao Zhou. Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications. J. Semicond., 2015, 36(4): 045009. doi: 10.1088/1674-4926/36/4/045009

[10]

Mingyuan Yu, Ting Li, Jiaqi Yang, Shuangshuang Zhang, Fujiang Lin, Lin He. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process. J. Semicond., 2016, 37(7): 075005. doi: 10.1088/1674-4926/37/7/075005

[11]

Wei Liu, Tingcun Wei, Bo Li, Lifeng Yang, Yongcai Hu. A reference voltage in capacitor-resister hybrid SAR ADC for front-end readout system of CZT detector. J. Semicond., 2016, 37(1): 015005. doi: 10.1088/1674-4926/37/1/015005

[12]

Yun Gui, Xu Zhang, Yuan Wang, Ming Liu, Weihua Pei, Kai Liang, Suibiao Huang, Bin Li, Hongda Chen. A multi-channel fully differential programmable integrated circuit for neural recording application. J. Semicond., 2013, 34(10): 105009. doi: 10.1088/1674-4926/34/10/105009

[13]

Liangbo Xie, Jiaxin Liu, Yao Wang, Guangjun Wen. A low-power CMOS smart temperature sensor for RFID application. J. Semicond., 2014, 35(11): 115002. doi: 10.1088/1674-4926/35/11/115002

[14]

Xiaofei Pu, Lei Wan, Hui Zhang, Yajie Qin, Zhiliang Hong. A low-power portable ECG sensor interface with dry electrodes. J. Semicond., 2013, 34(5): 055002. doi: 10.1088/1674-4926/34/5/055002

[15]

Tong Xingyuan, Zhu Zhangming, Yang Yintang. An offset cancellation technique in a switched-capacitor comparator for SAR ADCs. J. Semicond., 2012, 33(1): 015011. doi: 10.1088/1674-4926/33/1/015011

[16]

Shubin Liu, Zhangming Zhu, Yintang Yang, Lianxi Liu. A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC. J. Semicond., 2014, 35(5): 055008. doi: 10.1088/1674-4926/35/5/055008

[17]

Yang Siyu, Zhang Hui, Fu Wenhui, Yi Ting, Hong Zhiliang. A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator. J. Semicond., 2011, 32(3): 035002. doi: 10.1088/1674-4926/32/3/035002

[18]

Xue Han, Hua Fan, Qi Wei, Huazhong Yang. A high SFDR 6-bit 20-MS/s SAR ADC based on time-domain comparator. J. Semicond., 2013, 34(8): 085008. doi: 10.1088/1674-4926/34/8/085008

[19]

Fan Hua, Wei Qi, Kobenge Sekedi Bomeh, Yin Xiumei, Yang Huazhong. An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB. J. Semicond., 2010, 31(9): 095011. doi: 10.1088/1674-4926/31/9/095011

[20]

Weiru Gu, Yimin Wu, Fan Ye, Junyan Ren. A single-ended 10-bit 200 kS/s 607 μW SAR ADC with an auto-zeroing offset cancellation technique. J. Semicond., 2015, 36(10): 105006. doi: 10.1088/1674-4926/36/10/105006

Search

Advanced Search >>

GET CITATION

W Lü, D N Luo, F C Mei, J Q Yang, L B Yao, L He, F J Lin. A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS[J]. J. Semicond., 2014, 35(5): 055006. doi: 10.1088/1674-4926/35/5/055006.

Export: BibTex EndNote

Article Metrics

Article views: 696 Times PDF downloads: 12 Times Cited by: 0 Times

History

Manuscript received: 21 October 2013 Manuscript revised: 05 November 2013 Online: Published: 01 May 2014

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误