J. Semicond. > Volume 35 > Issue 8 > Article Number: 085007

A 0.6-V 8.3-ENOB asynchronous SAR ADC for biomedical applications

Yan Song , Zhongming Xue , Pengcheng Yan , Jueying Zhang and Li Geng ,

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Abstract: A microwatt asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power requirements of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.

Key words: SAR ADClow voltagelow powerbiomedical system

Abstract: A microwatt asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power requirements of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.

Key words: SAR ADClow voltagelow powerbiomedical system



References:

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Agnes A, Bonizzoni E, Malcovati P. A 9.4-ENOB 1 V 3.8μW 100 kS/s SAR ADC with time-domain comparator[J]. ISSCC, 2008, 12(5): 246.

[14]

Yang S Y, Zhang H, Fu W H. A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator[J]. Journal of Semiconductors, 2011, 32(1): 015001. doi: 10.1088/1674-4926/32/1/015001

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[1]

Harrison R R, Watkins P T, Kier R J. A low-power integrated circuit for a wireless 100-electrode neural recording system[J]. IEEE J Solid-State Circuits, 2007, 42(1): 123. doi: 10.1109/JSSC.2006.886567

[2]

Sin S W, U S P, Martins R P. Generalized low-voltage circuit techniques for very high-speed time-interleaved analog-to-digital converters. Dordrecht Heidelberg London New York: Springer, 2010

[3]

Pieter H, Eugenio C, Arthur van R. A 10 b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10.1 b ENOB at 2.2 fJ/Conversion-Step[J]. IEEE J Solid-State Circuits, 2013, 48(12): 3011. doi: 10.1109/JSSC.2013.2278471

[4]

Huang G Y, Chang S J, Liu C C. A 1-μW 10-bit 200-kS/s SAR ADC with a bypass window for biomedical applications[J]. IEEE J Solid-State Circuits, 2012, 47(11): 2783. doi: 10.1109/JSSC.2012.2217635

[5]

Qin L. Research and design of 11-bit SAR ADC based on reused terminating capacitor switching procedure. Master Thesis, Zhejiang University, 2012

[6]

Yu M, Wu L, Li F. An 8 bit 12 MS/s asynchronous successive approximation register ADC with an on-chip reference[J]. Journal of Semiconductors, 2013, 34(2): 25010. doi: 10.1088/1674-4926/34/2/025010

[7]

Zhu Y, Chan C H, Chio U F. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE J Solid-State Circuits, 2010, 45(6): 1111. doi: 10.1109/JSSC.2010.2048498

[8]

Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731. doi: 10.1109/JSSC.2010.2042254

[9]

Zhu Z M, Xiao Y, Song X L. VCM-based monotonic capacitor switching scheme for SAR ADC[J]. Electron Lett, 2013, 49(5): 327. doi: 10.1049/el.2012.3332

[10]

Zhang H, Qin Y J, Yang S Y. A 455 nW 220 fJ/conversion-step 12 bits 2 kS/s SAR ADC for portable biopotential acquisition systems[J]. Journal of Semiconductors, 2011, 32(1): 015001. doi: 10.1088/1674-4926/32/1/015001

[11]

Fan H, Wei Q, Kobenge S B. An 8-bit 180 kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB[J]. Journal of Semiconductors, 2010, 31(9): 095011. doi: 10.1088/1674-4926/31/9/095011

[12]

Hong H C, Lee G M. A 65-fJ/Conversion-Step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC[J]. IEEE J Solid-State Circuits, 2007, 42(10): 2161. doi: 10.1109/JSSC.2007.905237

[13]

Agnes A, Bonizzoni E, Malcovati P. A 9.4-ENOB 1 V 3.8μW 100 kS/s SAR ADC with time-domain comparator[J]. ISSCC, 2008, 12(5): 246.

[14]

Yang S Y, Zhang H, Fu W H. A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator[J]. Journal of Semiconductors, 2011, 32(1): 015001. doi: 10.1088/1674-4926/32/1/015001

[15]

Yuan C, Yvonne , Lam Y H. A 281-nW 43.3fJ/Conversion-Step 8-ENOB 25-kS/s asynchronous SAR ADC in 65 nm CMOS for biomedical applications[J]. ISCAS, 2013: 622.

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Y Song, Z M Xue, P C Yan, J Y Zhang, L Geng. A 0.6-V 8.3-ENOB asynchronous SAR ADC for biomedical applications[J]. J. Semicond., 2014, 35(8): 085007. doi: 10.1088/1674-4926/35/8/085007.

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History

Manuscript received: 30 December 2013 Manuscript revised: 08 March 2014 Online: Published: 01 August 2014

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