J. Semicond. > Volume 36 > Issue 10 > Article Number: 105003

A CMOS frontend chip for implantable neural recording with wide voltage supply range

Jialin Liu 1, 2, , Xu Zhang 1, , Xiaohui Hu 1, , Yatao Guo 2, , Peng Li 1, , Ming Liu 1, , Bin Li 2, and Hongda Chen 1,

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Abstract: A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper.The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC).The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a-3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device.A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain.The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz.The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s.The measured effective number of bits (ENOB) of the ADC is 8.7 bits.The entire circuit draws 165 to 216 μ<A current from the supply voltage varied from 1.34 to 3.3 V.The prototype chip is fabricated in the 0.18-m CMOS process and occupies an area of 1.23 mm2 (including pads).In-vitro recording was successfully carried out by the proposed frontend chip.

Key words: neural amplifierinstrumental amplifiercyclic analog-to-digital converterneural recording systemwide voltage supply range

Abstract: A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper.The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC).The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a-3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device.A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain.The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz.The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s.The measured effective number of bits (ENOB) of the ADC is 8.7 bits.The entire circuit draws 165 to 216 μ<A current from the supply voltage varied from 1.34 to 3.3 V.The prototype chip is fabricated in the 0.18-m CMOS process and occupies an area of 1.23 mm2 (including pads).In-vitro recording was successfully carried out by the proposed frontend chip.

Key words: neural amplifierinstrumental amplifiercyclic analog-to-digital converterneural recording systemwide voltage supply range



References:

[1]

Nurmikko A V, Donoghue J P, Hochberg L R. Listening to brain microcircuits for interfacing with external world—progress in wireless implantable microelectronic neuroengineering devices[J]. Proc IEEE, 2010, 98(3): 375.

[2]

Micera S, Citi L, Rigosa J. Decoding information from neural signals recorded using intraneural electrodes:toward the development of a neurocontrolled hand prosthesis[J]. Proc IEEE, 2010, 98(3): 407.

[3]

Harrison R R. The design of integrated circuits to observe brain activity[J]. Proc IEEE, 2008, 96(7): 74.

[4]

Chae M, Kim J, Liu W. Fully-differential self-biased biopotential amplifier[J]. Electron Lett, 2008, 44(24): 1390.

[5]

Perlin G E, Wise K D. An ultra-compact integrated front end for wireless neural recording microsystem[J]. IEEE J Microelectromechan Syst, 2010, 19(6): 1409.

[6]

Laughlin M M, Lu T, Dimitrijevic A. Towards a closed-loop implant system:application of embedded monitoring of periph-eral and central neural activity[J]. IEEE Trans Neural System and Rehabilitation Engineering, 2012, 20(4): 443.

[7]

Harrison R R, Charles C. A low-power low-noise CMOS amplifier for neural recording applications[J]. IEEE J Solid-State Circuits, 2003, 38(6): 958.

[8]

Zhang Xu, Pei Weihua, Huang Beiju. Low power CMOS preamplifier for neural recording application[J]. Journal of Semiconductors, 2010, 31(4): 045002.

[9]

Qian C, Parramon J, Sanchez-Sinencio E. A micropower lownoise neural recording front-end circuit for neural epileptic seizure detection[J]. IEEE J Solid-State Circuits, 2011, 46(6): 1392.

[10]

Wattanapanitch W, Fee M, Sarpeshkar R. An energy-efficient micropower neural recording amplifier[J]. IEEE Trans Biomedical Circuits and System, 2007, 1(2): 136.

[11]

Majidzadeh V, Schmid A, Leblebici Y. Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor[J]. IEEE Trans Biomedical Circuits and System, 2011, 5(3): 262.

[12]

Johson B, Molnar A. An orthogonal current-reuse amplifier for multi-channel sensing[J]. IEEE J Solid-State Circuits, 2013, 48(6): 1487.

[13]

Chaturvedi V, Amrutur B. An area-efficient noise-adaptive neural amplifier in 130 nm CMOS technology[J]. IEEE J Emerging and Selected Topics in Circuits and System, 2011, 1(4): 536.

[14]

Do A T, Tan Y, Lam C. Low power implantable neural recording front-end[J]. IEEE SoC Design Conference, International, 2012: 387.

[15]

Gui Yun, Zhang Xu, Wang Yuan. A multi-channel fully differential programmable integrated circuit for neural recording application[J]. Journal of Semiconductors, 2013, 34(10): 105009.

[16]

Abdelhalim K, Kokarovtseva L, Velazquez J L P. 915-MHz FSK/OOK wireless neural recording SoC with 64-channel signal FIR filters[J]. IEEE J Solid-State Circuits, 2013, 48(10): 2478.

[17]

Harrison R R, Kier R J, Chestek C. Wireless neural recording with single low-power integrated circuit[J]. IEEE Trans Neural Systems and Rehabilitation Engineering, 2009, 17(4): 322.

[18]

He Lenian, Wang Yi. Design and simulation of analog CMOS integrated circuits[J]. Science Press, 2008: 267.

[19]

Wang C C, Huang C C, Liou J S. A 140-dB CMRR lownoise instrumental amplifier for neural signal sensing[J]. IEEE Asia Pacific Conference on Circuits and System (APCCAC), 2006: 696.

[20]

Gao H, Walker R M, Nuyujukian P. A 96-channel full data rate direct neural interface in 0[J]. .

[21]

Wattanapanitch W, Sarpeshkar R. A low-power 32-channel digitally programmable neural recording integrated circuit[J]. IEEE Trans Biomedical Circuits and System, 2011, 5(6): 592.

[1]

Nurmikko A V, Donoghue J P, Hochberg L R. Listening to brain microcircuits for interfacing with external world—progress in wireless implantable microelectronic neuroengineering devices[J]. Proc IEEE, 2010, 98(3): 375.

[2]

Micera S, Citi L, Rigosa J. Decoding information from neural signals recorded using intraneural electrodes:toward the development of a neurocontrolled hand prosthesis[J]. Proc IEEE, 2010, 98(3): 407.

[3]

Harrison R R. The design of integrated circuits to observe brain activity[J]. Proc IEEE, 2008, 96(7): 74.

[4]

Chae M, Kim J, Liu W. Fully-differential self-biased biopotential amplifier[J]. Electron Lett, 2008, 44(24): 1390.

[5]

Perlin G E, Wise K D. An ultra-compact integrated front end for wireless neural recording microsystem[J]. IEEE J Microelectromechan Syst, 2010, 19(6): 1409.

[6]

Laughlin M M, Lu T, Dimitrijevic A. Towards a closed-loop implant system:application of embedded monitoring of periph-eral and central neural activity[J]. IEEE Trans Neural System and Rehabilitation Engineering, 2012, 20(4): 443.

[7]

Harrison R R, Charles C. A low-power low-noise CMOS amplifier for neural recording applications[J]. IEEE J Solid-State Circuits, 2003, 38(6): 958.

[8]

Zhang Xu, Pei Weihua, Huang Beiju. Low power CMOS preamplifier for neural recording application[J]. Journal of Semiconductors, 2010, 31(4): 045002.

[9]

Qian C, Parramon J, Sanchez-Sinencio E. A micropower lownoise neural recording front-end circuit for neural epileptic seizure detection[J]. IEEE J Solid-State Circuits, 2011, 46(6): 1392.

[10]

Wattanapanitch W, Fee M, Sarpeshkar R. An energy-efficient micropower neural recording amplifier[J]. IEEE Trans Biomedical Circuits and System, 2007, 1(2): 136.

[11]

Majidzadeh V, Schmid A, Leblebici Y. Energy efficient low-noise neural recording amplifier with enhanced noise efficiency factor[J]. IEEE Trans Biomedical Circuits and System, 2011, 5(3): 262.

[12]

Johson B, Molnar A. An orthogonal current-reuse amplifier for multi-channel sensing[J]. IEEE J Solid-State Circuits, 2013, 48(6): 1487.

[13]

Chaturvedi V, Amrutur B. An area-efficient noise-adaptive neural amplifier in 130 nm CMOS technology[J]. IEEE J Emerging and Selected Topics in Circuits and System, 2011, 1(4): 536.

[14]

Do A T, Tan Y, Lam C. Low power implantable neural recording front-end[J]. IEEE SoC Design Conference, International, 2012: 387.

[15]

Gui Yun, Zhang Xu, Wang Yuan. A multi-channel fully differential programmable integrated circuit for neural recording application[J]. Journal of Semiconductors, 2013, 34(10): 105009.

[16]

Abdelhalim K, Kokarovtseva L, Velazquez J L P. 915-MHz FSK/OOK wireless neural recording SoC with 64-channel signal FIR filters[J]. IEEE J Solid-State Circuits, 2013, 48(10): 2478.

[17]

Harrison R R, Kier R J, Chestek C. Wireless neural recording with single low-power integrated circuit[J]. IEEE Trans Neural Systems and Rehabilitation Engineering, 2009, 17(4): 322.

[18]

He Lenian, Wang Yi. Design and simulation of analog CMOS integrated circuits[J]. Science Press, 2008: 267.

[19]

Wang C C, Huang C C, Liou J S. A 140-dB CMRR lownoise instrumental amplifier for neural signal sensing[J]. IEEE Asia Pacific Conference on Circuits and System (APCCAC), 2006: 696.

[20]

Gao H, Walker R M, Nuyujukian P. A 96-channel full data rate direct neural interface in 0[J]. .

[21]

Wattanapanitch W, Sarpeshkar R. A low-power 32-channel digitally programmable neural recording integrated circuit[J]. IEEE Trans Biomedical Circuits and System, 2011, 5(6): 592.

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J L Liu, X Zhang, X H Hu, Y T Guo, P Li, M Liu, B Li, H D Chen. A CMOS frontend chip for implantable neural recording with wide voltage supply range[J]. J. Semicond., 2015, 36(10): 105003. doi: 10.1088/1674-4926/36/10/105003.

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Manuscript received: 19 March 2015 Manuscript revised: Online: Published: 01 October 2015

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