J. Semicond. > Volume 36 > Issue 11 > Article Number: 114003

Simulation and research on a 4T-cell based duplication redundancy SRAM for SEU radiation hardening

Xinhong Hong 1, , , Liyang Pan 1, , , Wendi Zhang 1, , Dongmei Ji 2, , Dong Wu 1, , Chen Shen 2, and Jun Xu 1,

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Abstract: A novel 4T-cell based duplication redundancy SRAM is proposed for SEU radiation hardening applications. The memory cell is designed with a 65-nm low leakage process; the operation principle and the SEU radiation hardening mechanism are discussed in detail. The SEE characteristics and failure mechanism are also studied with a 3-D device simulator. The results show that the proposed SRAM structure exhibits high SEU hardening performance with a small cell size.

Key words: SRAMSEESEUradiation hardening3-D simulation

Abstract: A novel 4T-cell based duplication redundancy SRAM is proposed for SEU radiation hardening applications. The memory cell is designed with a 65-nm low leakage process; the operation principle and the SEU radiation hardening mechanism are discussed in detail. The SEE characteristics and failure mechanism are also studied with a 3-D device simulator. The results show that the proposed SRAM structure exhibits high SEU hardening performance with a small cell size.

Key words: SRAMSEESEUradiation hardening3-D simulation



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[1]

Shivakumar P, Kistler M, Keckler S W. Modeling the effect of technology trends on the soft error rate of combinational logic[J]. Int Con on Dependable Systems and Networks, 2002: 389.

[2]

Hazucha P, Svensson C. Impact of CMOS technology scaling on the atmospheric neutron soft error rate[J]. IEEE Trans Nucl Sci, 2000, 47(6): 2586.

[3]

Li T, Yang H, Cai G. A CMOS triple inter-locked latch for SEU insensitivity design[J]. IEEE Trans Nucl Sci, 2014, 61(6): 3265.

[4]

Dodd P E, Shaneyfelt M R, Felix J A. Production and propagation of single-event transients in high-speed digital logic ICs[J]. IEEE Trans Nucl Sci, 2004, 51(6): 3278.

[5]

Giot D, Roche P, Gasiot G. Heavy ion testing and 3D simulations of multiple cell upset in 65-nm standard SRAMs[J]. 9th Euro Conf on Radiation and Its Effects on Components and Systems, 2007: 1.

[6]

Haddad N F, Kelly A T, Lawrence R K. Incremental enhancement of SEU hardened 90 nm CMOS memory cell[J]. IEEE Trans Nucl Sci, 2011, 58(3): 975.

[7]

Nicolaidis M, Perez R, Alexandrescu D. Low-cost highly-robust hardened cells using blocking feedback transistors[J]. 26th IEEE VLSI Test Symposium, 2008: 371.

[8]

Lin S, Kim Y B, Lombardi F. A novel design technique for soft error hardening of nanoscale CMOS memory[J]. 52nd IEEE Int Midwest Symp on Circuits and Systems, 2009: 679.

[9]

Calin T, Nicolaidis M, Velazco R. Upset hardened memory design for submicron CMOS technology[J]. IEEE Trans Nucl Sci, 1996, 43(6): 2874.

[10]

Kim N S, Draper S C, Zhou S T. Analyzing the impact of joint optimization of cell size, redundancy, and ECC on low-voltage SRAM array total area[J]. IEEE Trans Very Large Scale Integration Syst, 2012, 20(12): 2333.

[11]

http://www . cogenda[J]. .

[12]

Bonacini S, Valerio P, Avramidou R. Characterization of a commercial 65-nm CMOS technology for SLHC applications[J]. Journal of Instrumentation, 2012, 7(1): 1.

[13]

Petersen E L, Pickel J C, Adams J H. Rate prediction for single event effects——a critique[J]. IEEE Trans Nucl Sci, 1992, 39(6): 1577.

[14]

Adams J H. Cosmic ray effects on microelectronics[J]. Naval Research Laboratory.

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X H Hong, L Y Pan, W D Zhang, D M Ji, D Wu, C Shen, J Xu. Simulation and research on a 4T-cell based duplication redundancy SRAM for SEU radiation hardening[J]. J. Semicond., 2015, 36(11): 114003. doi: 10.1088/1674-4926/36/11/114003.

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Manuscript received: 11 June 2015 Manuscript revised: Online: Published: 01 November 2015

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