J. Semicond. > Volume 36 > Issue 11 > Article Number: 114009

Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM

Yinhong Luo , , Fengqi Zhang , Hongxia Guo , Yao Xiao , Wen Zhao , Lili Ding and Yuanming Wang

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Abstract: Single event multiple-cell upsets (MCU) increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.

Key words: multiple-cell upsetsnanometer-scale SRAMtest factorsdevice orientation

Abstract: Single event multiple-cell upsets (MCU) increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.

Key words: multiple-cell upsetsnanometer-scale SRAMtest factorsdevice orientation



References:

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[1]

Correas V, Saigné F, Sagnes B. Prediction of multiple cell upset induced by heavy ions in a 90 nm bulk SRAM[J]. IEEE Trans Nucl Sci, 2009, 65(4): 2050.

[2]

Lawrence R K, Kelly A T. Single event effect induced multiple-cell upsets in a commercial 90 nm CMOS digital technology[J]. IEEE Trans Nucl Sci, 2008, 55(6): 3367.

[3]

Giot D, Roche P, Gasiot G. Heavy ion testing and 3-D simulations of multiple cell upset in 65 nm standard SRAMs[J]. IEEE Trans Nucl Sci, 2008, 55(4): 2048.

[4]

Tipon A D, Pellish J A, Hutson J M. Device-orientation effects on multiple-bit upset in 65 nm SRAMs[J]. IEEE Trans Nucl Sci, 2008, 56(6): 2880.

[5]

Amusan O A, Massengill L W, Baze M P. Directional sensitivity of single event upsets in 90 nm CMOS due to charge sharing[J]. IEEE Trans Nucl Sci, 2007, 54(6): 2584.

[6]

Amusan O A, Witulski A F, Massengill L W. Charge collection and charge sharing in a 130 nm CMOS technology[J]. IEEE Trans Nucl Sci, 2006, 53(6): 3253.

[7]

Giot D, Roche P, Gasiot G. Multiple-bit upset analysis in 90 nm SRAMs: heavy ions testing and 3D simulations[J]. IEEE Trans Nucl Sci, 2007, 54(6): 904.

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Y H Luo, F Q Zhang, H X Guo, Y Xiao, W Zhao, L L Ding, Y M Wang. Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM[J]. J. Semicond., 2015, 36(11): 114009. doi: 10.1088/1674-4926/36/11/114009.

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Manuscript received: 11 June 2015 Manuscript revised: Online: Published: 01 November 2015

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