J. Semicond. > Volume 36 > Issue 11 > Article Number: 115004

The investigation on sensitive mapping of memory cell in microprocessor

Chunqing Yu 1, , , Long Fan 1, , Suge Yue 1, 2, , Maoxin Chen 1, , Shougang Du 1, and Hongchao Zheng 1,

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Abstract: The single event effects of the sensitivity of a circuit are investigated on a 32-bit microprocessor with a five-stage instruction pipeline by pulsed laser test. The investigation on sensitive mapping of the memory cell is illustrated and then the comparison between the sensitive mapping and the layout of the circuit is made. A comparison result indicates that the area of the sensitive node in sensitive mapping is just the location of the drain in the layout. Therefore, SEE sensitivity in sensitive mapping fits well with that in the physical layout of functional units, which can directly and objectively indicate the size and distribution of sensitive areas. The investigation of sensitive mapping is a meaningful way to verify the hardened effect and provide a reference for improving hardened design by combining with the physical layout.

Key words: single event effectsmemory cellsmicroprocessorsensitive mapping

Abstract: The single event effects of the sensitivity of a circuit are investigated on a 32-bit microprocessor with a five-stage instruction pipeline by pulsed laser test. The investigation on sensitive mapping of the memory cell is illustrated and then the comparison between the sensitive mapping and the layout of the circuit is made. A comparison result indicates that the area of the sensitive node in sensitive mapping is just the location of the drain in the layout. Therefore, SEE sensitivity in sensitive mapping fits well with that in the physical layout of functional units, which can directly and objectively indicate the size and distribution of sensitive areas. The investigation of sensitive mapping is a meaningful way to verify the hardened effect and provide a reference for improving hardened design by combining with the physical layout.

Key words: single event effectsmemory cellsmicroprocessorsensitive mapping



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[1]

Melinger J S, Buchner S, McMorrow D. Crirical evaluation of the pulsed laser method for single event effects testing and fundamental studies[J]. IEEE Trans Nucl Sci, 1994, 41(6): 2574.

[2]

Jones R, Chugg A M, Jones C M S. Comparison between SRAM SEE cross-sections from ion beam testing with those obtained using a new picosecond pulsed laser facility[J]. IEEE Trans Nucl Sci, 2000, 47(3): 539.

[3]

Lei Zhifeng. Single event effects test for CMOS devices using 1064 nm pulsed laser[J]. International Conference on Quality, Reliability, Risk, Maintenance, and Safety Engineering, Xi'an, China, 2011: 325.

[4]

Feng Guoqiang, Shangguan Shipeng, Ma Yingqi. SEE characteristics of small feature size circuits by using laser backside testing[J]. Journal of Semiconductors, 2012, 33(1): 014008.

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C Q Yu, L Fan, S G Yue, M X Chen, S G Du, H C Zheng. The investigation on sensitive mapping of memory cell in microprocessor[J]. J. Semicond., 2015, 36(11): 115004. doi: 10.1088/1674-4926/36/11/115004.

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Manuscript received: 11 June 2015 Manuscript revised: Online: Published: 01 November 2015

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