J. Semicond. > Volume 36 > Issue 11 > Article Number: 115007

A four-interleaving HBD SRAM cell based on dual DICE for multiple node collection mitigation

Lin Liu 1, , , Suge Yue 1, 2, and Shijin Lu 1,

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Abstract: A 4-interleaving cell of 2-dual interlocked cells (DICE) is proposed, which reduces single event induced multiple node collection between the sensitive nodes of sensitive pairs in a DICE storage cell in 65 nm technology. The technique involves the 4-interleaving of dual DICE cells at a layout level to meet the required spacing between sensitive nodes in an area-efficient manner. Radiation experiments using a 65 nm CMOS test chip demonstrate that the LETth of our 4-interleaving cell of dual DICE encounters are almost 4× larger and the SEU cross section per bit for our proposed dual DICE design is almost two orders of magnitude less compared to the reference traditional DICE cell.

Key words: single event upset (SEU)hardened-by-design (HBD)multi-node upset (MNU)

Abstract: A 4-interleaving cell of 2-dual interlocked cells (DICE) is proposed, which reduces single event induced multiple node collection between the sensitive nodes of sensitive pairs in a DICE storage cell in 65 nm technology. The technique involves the 4-interleaving of dual DICE cells at a layout level to meet the required spacing between sensitive nodes in an area-efficient manner. Radiation experiments using a 65 nm CMOS test chip demonstrate that the LETth of our 4-interleaving cell of dual DICE encounters are almost 4× larger and the SEU cross section per bit for our proposed dual DICE design is almost two orders of magnitude less compared to the reference traditional DICE cell.

Key words: single event upset (SEU)hardened-by-design (HBD)multi-node upset (MNU)



References:

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[1]

Olson B D, Ball D R, Warren K M. Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design[J]. IEEE Trans Nucl Sci, 2005, 52: 2132.

[2]

Amusan O A, Sternberg A L. Single event upsets in a 130 nm hardened latch design due to charge sharing[J]. Proc 45th Int Reliability Physics Symp, Arizona, 2007: 306.

[3]

Black J D, Sternberg A L. Multiple-bit upset in 130 nm CMOS technology[J]. IEEE Trans Nucl Sci, 2005, 52(6): 2536.

[4]

Amusan O A, Witulski A F. Charge collection and charge sharing in a 130 nm CMOS technology[J]. IEEE Trans Nucl Sci, 2006, 53(6): 3253.

[5]

Olson B D, Amusan O A, Dasgupta S. Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology[J]. IEEE Trans Nucl Sci, 2007, 54(4): 894.

[6]

Amusan O A, Massengill L W. Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process[J]. IEEE CFP08RPS-CDR 46th Annual International Reliability Physics Symposium, Phoenix, 2008.

[7]

Black J D, Sternberg A L. HBD layout isolation techniques for multiple node charge collection mitigation[J]. IEEE Trans Nucl Sci, 2005, 52(6): 2536.

[8]

Haghi M, Draper J. The 90 nm double-DICE storage element to reduce single-event upsets[J]. IEEE Midwest Symposium on Circuits and Systems, 2009: 463.

[9]

Chen T H, Chen J, Clark L T. Ultra-low power radiation hardened by design memory circuits[J]. IEEE Trans Nucl Sci, 2007, 54(6): 2004.

[10]

Liu L, Zhao Y, Yue S. 3D simulation of charge collection and MNU in SEU hardened storage cells[J]. 10th European Conference on Radiation and Its Effects in Component and Systems, 2009: 230.

[11]

Chen S, Ding G. A framework for fully-physical, statistically-enhanced Monte-Carlo simulation of SEU[J]. RADECS, 2012.

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L Liu, S G Yue, S J Lu. A four-interleaving HBD SRAM cell based on dual DICE for multiple node collection mitigation[J]. J. Semicond., 2015, 36(11): 115007. doi: 10.1088/1674-4926/36/11/115007.

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Manuscript received: 11 June 2015 Manuscript revised: Online: Published: 01 November 2015

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