J. Semicond. > Volume 36 > Issue 4 > Article Number: 045007

A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors

Wei Liu , , Tingcun Wei , Bo Li , Panjie Guo and Yongcai Hu

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Abstract: This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) for multi-channel CdZnTe (CZT) detector applications. In order to improve the SAR-ADC's accuracy, a novel comparator is proposed in which the offset voltage is self-calibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4M CMOS process. At a 3.3/5 V power supply and a sampling rate of 1 MS/s, the proposed SAR-ADC achieves a peak signal to noise and distortion ratio (SINAD) of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 × 1080 μm2.

Key words: SARADCradiation-hardnesslow powerCZT detectors

Abstract: This paper presents a low power, area-efficient and radiation-hardened 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) for multi-channel CdZnTe (CZT) detector applications. In order to improve the SAR-ADC's accuracy, a novel comparator is proposed in which the offset voltage is self-calibrated and also a new architecture for the unit capacitor array is proposed to reduce the capacitance mismatches in the charge-redistribution DAC. The ability to radiation-harden the SAR-ADC is enhanced through circuit and layout design technologies. The prototype chip was fabricated using a TSMC 0.35 μm 2P4M CMOS process. At a 3.3/5 V power supply and a sampling rate of 1 MS/s, the proposed SAR-ADC achieves a peak signal to noise and distortion ratio (SINAD) of 67.64 dB and consumes only 10 mW power. The core of the prototype chip occupies an active area of 1180 × 1080 μm2.

Key words: SARADCradiation-hardnesslow powerCZT detectors



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Li Quanliang, Liu Liyuan, Han Ye. A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors[J]. Journal of Semiconductors, 2014, 35(10): 105008.

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Lü Wei, Luo Duona, Mei Fengcheng. A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS[J]. Journal of Semiconductors, 2014, 35(5): 055006.

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Han Xue, Wei Qi, Yang Huazhong. A single channel, 6-bit 230-MS/s asynchronous SAR ADC based on 2 bits/stage[J]. Journal of Semiconductors, 2014, 35(7): 075005.

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Otfinowski P. A 2.5 MS/s 225 μW 8-bit charge redistribution SAR-ADC for multichannel applications[J]. 17th International Conference Mixed Design of Integrated Circuits and Systems, 2010: 182.

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Allen P E, Holberg D R. Holberg D R. CMOS analog circuit design[J]. 2nd ed. Electronics Industry Press, 2005: 630.

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Pei Xiaomin, Wang Peiyuan. Design and modeling of a 12-bit SAR-ADC IP with non-lump capacitor array[J]. 2nd International Conference on Future Computer and Communication, 2010.

[15]

Pun K, Sun L, Li B. Unit capacitor array based SAR ADC[J]. Microelectron Reliab, 2013, 53(3): 505.

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[1]

Gao W, Gao D, Hu-Guo C. Design of a 12-bit 2.5 MS/s integrated multi-channel single-ramp analog-to-digital converter for imaging detector systems[J]. IEEE Trans Instrum Meas, 2011, 60(6): 1942.

[2]

Gao W, Gao D, Gan B. A novel data acquisition scheme based on a low-noise front-end ASIC and a high-speed ADC for CZT-based PET imaging[J]. 18th IEEE-NPSS, 2012.

[3]

Lim S, Lee J, Kim D. A high-speed CMOS image sensor with column-parallel two-step single-slope ADCs[J]. IEEE Trans Electron Devices, 2009, 56(3): 393.

[4]

Rossini A, Caccia S, Bertuccio G. A complete read-out channel with embedded Wilkinson A/D converter for X-ray spectrometry[J]. IEEE Trans Nucl Sci, 2007, 54(4): 1216.

[5]

Delagnes E, Breton D, Lugie F Z. A low power multi-channel single ramp ADC with up to 3.2 GHz virtual clock[J]. IEEE Trans Nucl Sci, 2007, 54(5): 1735.

[6]

Li Quanliang, Liu Liyuan, Han Ye. A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors[J]. Journal of Semiconductors, 2014, 35(10): 105008.

[7]

Lü Wei, Luo Duona, Mei Fengcheng. A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS[J]. Journal of Semiconductors, 2014, 35(5): 055006.

[8]

Han Xue, Wei Qi, Yang Huazhong. A single channel, 6-bit 230-MS/s asynchronous SAR ADC based on 2 bits/stage[J]. Journal of Semiconductors, 2014, 35(7): 075005.

[9]

Fang X C, Hu-Guo C, Ollivier-Henry N. Design of a multi-channel front-end readout ASIC with low noise and large dynamic input range for APD-based PET imaging[J]. IEEE Trans Nucl Sci, 2009, 56(4): 2351.

[10]

Gevin O, Baron P, Coppolani X. IDeF-X ECLAIRs: a CMOS ASIC for the readout of CdTe and CdZnTe detectors for high resolution spectroscopy[J]. IEEE Trans Nucl Sci, 2010, 57(3): 1015.

[11]

De Geronimo G, O'Connor P, Grosholz J. A generation of CMOS readout ASICs for CZT detectors[J]. IEEE Trans Nucl Sci, 2000, 47: 1857.

[12]

Otfinowski P. A 2.5 MS/s 225 μW 8-bit charge redistribution SAR-ADC for multichannel applications[J]. 17th International Conference Mixed Design of Integrated Circuits and Systems, 2010: 182.

[13]

Allen P E, Holberg D R. Holberg D R. CMOS analog circuit design[J]. 2nd ed. Electronics Industry Press, 2005: 630.

[14]

Pei Xiaomin, Wang Peiyuan. Design and modeling of a 12-bit SAR-ADC IP with non-lump capacitor array[J]. 2nd International Conference on Future Computer and Communication, 2010.

[15]

Pun K, Sun L, Li B. Unit capacitor array based SAR ADC[J]. Microelectron Reliab, 2013, 53(3): 505.

[16]

Anelli G, Campbell M, Delmastro M. Radiation tolerant VLSI circuits in standard deep submicron CMOS technologies for the LHC experiments: practical design aspects[J]. IEEE Trans Nucl Sci, 1999, 46(6): 1690.

[17]

Lee C I, Johnston A H. Comparison of total dose responses on high resolution analog-to-digital converter technologies[J]. IEEE Trans Nucl Sci, 1998, 45: 1444.

[18]

Dulinski W. Ultra-thin tracking detectors for ILC and other applications[J]. Course, IPHC, 2007.

[19]

Analog Devices Technologies. 16-Channel, 1MS/s, 12bit ADC with Sequencer in 28-Lead TSSOP[J]. The datasheet of AD7490-EP.

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W Liu, T C Wei, B Li, P J Guo, Y C Hu. A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors[J]. J. Semicond., 2015, 36(4): 045007. doi: 10.1088/1674-4926/36/4/045007.

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History

Manuscript received: 23 September 2014 Manuscript revised: Online: Published: 01 April 2015

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