J. Semicond. > Volume 36 > Issue 4 > Article Number: 045009

Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications

Hui Hong , , Shiliang Li and Tao Zhou

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Abstract: This paper presents a low power 10 bit 300 ksps successive approximation register analog-to-digital converter (SAR ADC) which is applied in wireless sensor network (WSN) applications. A single ended energy-saving split capacitor DAC array and a latch comparator with a rail to rail input stage are utilized to implement the ADC, which can reduce power dissipation while expanding the full scale input range and improve the signal-to-noise ratio (SNR). For power optimization the supply voltage of the SAR ADC is designed to be as low as 2 V. Four analog input channels are designed which make the ADC more suitable for WSN applications. The prototype circuit is fabricated using 3.3 V, 0.35 μm 2P4M CMOS technology and occupies an active chip area of 1.23 mm2. The test results show that the power dissipation is only 200 μW at a 2 V power supply and a sampling rate of 166 kSps. The calculated SNR is 58.25 dB, the ENOB is 9.38 bit and the FOM is 4.95 pJ/conversion-step.

Key words: low powermulti-channelsSAR ADCWSNsplit capacitor array

Abstract: This paper presents a low power 10 bit 300 ksps successive approximation register analog-to-digital converter (SAR ADC) which is applied in wireless sensor network (WSN) applications. A single ended energy-saving split capacitor DAC array and a latch comparator with a rail to rail input stage are utilized to implement the ADC, which can reduce power dissipation while expanding the full scale input range and improve the signal-to-noise ratio (SNR). For power optimization the supply voltage of the SAR ADC is designed to be as low as 2 V. Four analog input channels are designed which make the ADC more suitable for WSN applications. The prototype circuit is fabricated using 3.3 V, 0.35 μm 2P4M CMOS technology and occupies an active chip area of 1.23 mm2. The test results show that the power dissipation is only 200 μW at a 2 V power supply and a sampling rate of 166 kSps. The calculated SNR is 58.25 dB, the ENOB is 9.38 bit and the FOM is 4.95 pJ/conversion-step.

Key words: low powermulti-channelsSAR ADCWSNsplit capacitor array



References:

[1]

Mrkovic B, Asenbrener M. A 10-b fully differential CMOS SAR ADC for wireless sensor networks[J]. Proceedings of the 34th International Convention on MIPRO, 2011: 76.

[2]

Verma N, Chandrakasan A. A 25 μW 100 kS/s 12 b ADC for wireless micro-sensor applications[J]. ISSCC Dig Tech Papers, 2006: 222.

[3]

Chang Y K, Wang C S, Wang C K. A 8-bit 500-KS/s low power SAR ADC for bio-medical application[J]. ISSCC, 2007: 228.

[4]

Van Elzakker M, van Tuijl E, Geraedts P. A 1.9 μW 4.4 fJ/conversion-step 10 b 1 MS/s charge redistribution ADC[J]. ISSCC Dig Tech Papers, 2008: 244.

[5]

Craninckx J, van der Plas G. A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS[J]. ISSCC Dig Tech Papers, 2007: 246.

[6]

Giannini V, Nuzzo P, Chironi V. An 820 μW 9 b 40 MS/s noise-tolerant dynamic SAR ADC in 90 nm digital CMOS[J]. ISSCC Dig Tech Papers, 2008: 238.

[7]

Chen H W, Liu Y H, Lin Y H. A 3 mW 12 b 10 MS/s sub-range SAR ADC[J]. IEEE Asian Solid-State Circuits Conference, 2009: 153.

[8]

Hong H, Li S L, Liu S. Design of a low power multi-channel 10 bit SARADC[J]. Appl Mechan Mater, 2014: 4576.

[9]

Wang L, Ren J Y, Yin W J. A high-speed high-resolution low-distortion CMOS Bootstrapped switch[J]. IEEE International Symposium on Circuits and Systems, 2007: 1722.

[10]

Qian L B, Zhu Z M, Yang Y T. A low distortion CMOS Bootstrapped switch[J]. Pacific-Asia Conference on Circuits, Communications and Systems, 2009: 1109.

[11]

Kamalinejad P, Mirabbasi S, Leung V C. An ultra-low-power SAR ADC with an area-efficient DAC architecture[J]. IEEE International Symposium on Circuits and Systems (ISCAS), 2011: 13.

[12]

Rivoir R, Maloberti F. A 1 mV resolution, 10 MS/s rail-to-rail comparator in 0.5 μm low voltage CMOS digital technology[J]. IEEE International Symposium on Circuit and Systems, 1997: 461.

[13]

Pei X, Zhang J. Design and optimization on the interior DAC of SAR ADC[J]. China Academic Journal Electronic Publishing House, 2012: 654.

[14]

Andreatos A S, Zagorianos A. Matlab GUI application for teaching control systems[J]. Proceedings of the 6th WSEAS International Conference on Engineering Education, 2009: 208.

[15]

Cadence Corp. Cadence Modelwriter Reference, Cadence Design System[J]. Cadence Design System, 2005-16.

[16]

Maxim Cooperation, Selecting the Optimum. Test Tones and Test Equipment for Successful High-Speed ADC Sine-wave Testing,[J]. .

[17]

Maxim, Histogram, http://www. maximintegrated[J]. , 2005.

[18]

Zhong L, Yang H, Zhang C. Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC[J]. 7th International Conference on ASIC, 2007: 668.

[19]

Jun C, Feng R, Xu M H. IC design of 2 Ms/s 10-bit SAR ADC with low power[J]. International Symposium on High Density packaging and Microsystem Integration, 2007: 1.

[20]

Confalonleri P, Zarnprogno M, Girardi F. A 2.7 mW 1 MSps 10 b analog-to-digital converter with built-in reference buffer and 1 LSB accuracy programmable input ranges[J]. Proceedings ESSCIRC, 2004-255.

[21]

Raj G, Gupta A, Gupta A. Self timed high speed 8-bit SAR ADC in 0.35 μm[J]. Annual IEEE India Conference (INDICON), 2013: 1.

[1]

Mrkovic B, Asenbrener M. A 10-b fully differential CMOS SAR ADC for wireless sensor networks[J]. Proceedings of the 34th International Convention on MIPRO, 2011: 76.

[2]

Verma N, Chandrakasan A. A 25 μW 100 kS/s 12 b ADC for wireless micro-sensor applications[J]. ISSCC Dig Tech Papers, 2006: 222.

[3]

Chang Y K, Wang C S, Wang C K. A 8-bit 500-KS/s low power SAR ADC for bio-medical application[J]. ISSCC, 2007: 228.

[4]

Van Elzakker M, van Tuijl E, Geraedts P. A 1.9 μW 4.4 fJ/conversion-step 10 b 1 MS/s charge redistribution ADC[J]. ISSCC Dig Tech Papers, 2008: 244.

[5]

Craninckx J, van der Plas G. A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS[J]. ISSCC Dig Tech Papers, 2007: 246.

[6]

Giannini V, Nuzzo P, Chironi V. An 820 μW 9 b 40 MS/s noise-tolerant dynamic SAR ADC in 90 nm digital CMOS[J]. ISSCC Dig Tech Papers, 2008: 238.

[7]

Chen H W, Liu Y H, Lin Y H. A 3 mW 12 b 10 MS/s sub-range SAR ADC[J]. IEEE Asian Solid-State Circuits Conference, 2009: 153.

[8]

Hong H, Li S L, Liu S. Design of a low power multi-channel 10 bit SARADC[J]. Appl Mechan Mater, 2014: 4576.

[9]

Wang L, Ren J Y, Yin W J. A high-speed high-resolution low-distortion CMOS Bootstrapped switch[J]. IEEE International Symposium on Circuits and Systems, 2007: 1722.

[10]

Qian L B, Zhu Z M, Yang Y T. A low distortion CMOS Bootstrapped switch[J]. Pacific-Asia Conference on Circuits, Communications and Systems, 2009: 1109.

[11]

Kamalinejad P, Mirabbasi S, Leung V C. An ultra-low-power SAR ADC with an area-efficient DAC architecture[J]. IEEE International Symposium on Circuits and Systems (ISCAS), 2011: 13.

[12]

Rivoir R, Maloberti F. A 1 mV resolution, 10 MS/s rail-to-rail comparator in 0.5 μm low voltage CMOS digital technology[J]. IEEE International Symposium on Circuit and Systems, 1997: 461.

[13]

Pei X, Zhang J. Design and optimization on the interior DAC of SAR ADC[J]. China Academic Journal Electronic Publishing House, 2012: 654.

[14]

Andreatos A S, Zagorianos A. Matlab GUI application for teaching control systems[J]. Proceedings of the 6th WSEAS International Conference on Engineering Education, 2009: 208.

[15]

Cadence Corp. Cadence Modelwriter Reference, Cadence Design System[J]. Cadence Design System, 2005-16.

[16]

Maxim Cooperation, Selecting the Optimum. Test Tones and Test Equipment for Successful High-Speed ADC Sine-wave Testing,[J]. .

[17]

Maxim, Histogram, http://www. maximintegrated[J]. , 2005.

[18]

Zhong L, Yang H, Zhang C. Design of an embedded CMOS CR SAR ADC for low power applications in bio-sensor SOC[J]. 7th International Conference on ASIC, 2007: 668.

[19]

Jun C, Feng R, Xu M H. IC design of 2 Ms/s 10-bit SAR ADC with low power[J]. International Symposium on High Density packaging and Microsystem Integration, 2007: 1.

[20]

Confalonleri P, Zarnprogno M, Girardi F. A 2.7 mW 1 MSps 10 b analog-to-digital converter with built-in reference buffer and 1 LSB accuracy programmable input ranges[J]. Proceedings ESSCIRC, 2004-255.

[21]

Raj G, Gupta A, Gupta A. Self timed high speed 8-bit SAR ADC in 0.35 μm[J]. Annual IEEE India Conference (INDICON), 2013: 1.

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H Hong, S L Li, T Zhou. Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications[J]. J. Semicond., 2015, 36(4): 045009. doi: 10.1088/1674-4926/36/4/045009.

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Manuscript received: 18 July 2014 Manuscript revised: Online: Published: 01 April 2015

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