J. Semicond. > Volume 36 > Issue 5 > Article Number: 054002

A 2-D semi-analytical model of double-gate tunnel field-effect transistor

Huifang Xu , Yuehua Dai , , Ning Li and Jianbin Xu

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Abstract: A 2-D semi-analytical model of double gate (DG) tunneling field-effect transistor (TFET) is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane's model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.

Key words: semi-analytical methodeigenfunction expansion methoddouble-gate tunnel field effect transistor (TFET)surface potentialdrain current

Abstract: A 2-D semi-analytical model of double gate (DG) tunneling field-effect transistor (TFET) is proposed. By aid of introducing two rectangular sources located in the gate dielectric layer and the channel, the 2-D Poisson equation is solved by using a semi-analytical method combined with an eigenfunction expansion method. The expression of the surface potential is obtained, which is a special function for the infinite series expressions. The influence of the mobile charges on the potential profile is taken into account in the proposed model. On the basis of the potential profile, the shortest tunneling length and the average electrical field can be derived, and the drain current is then constructed by using Kane's model. In particular, the changes of the tunneling parameters Ak and Bk influenced by the drain-source voltage are also incorporated in the predicted model. The proposed model shows a good agreement with TCAD simulation results under different drain-source voltages, silicon film thicknesses, gate dielectric layer thicknesses, and gate dielectric layer constants. Therefore, it is useful to optimize the DG TFET and this provides a physical insight for circuit level design.

Key words: semi-analytical methodeigenfunction expansion methoddouble-gate tunnel field effect transistor (TFET)surface potentialdrain current



References:

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Verhulst A S, Sorée B, Leonelli D. Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor[J]. J Appl Phys, 2010, 107: 024518.

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Gholizadeh M, Hosseini S E. A 2-D analytical model for double-gate tunnel FETs[J]. IEEE Trans Electron Devices, 2014, 61(5): 1494.

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Xie Q, Xu J, Taur Y. Review and critique of analytic models of MOSFET short-channel effects in subthreshold[J]. IEEE Trans Electron Devices, 2012, 59(6): 1569.

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Lee M J, Choi W Y. Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs)[J]. Solid-State Electron, 2011, 63: 110.

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[16]

Wan J, Royer C L, Zaslavsky A. Tunneling FETs on SOI: suppression of ambipolar leakage, low-frequency noise behavior, and modeling[J]. Solid-State Electron, 2011, 65.

[17]

Bhushan B, Nayak K, Rao V R. DC compact model for SOI tunnel field-effect transistors[J]. IEEE Trans Electron Devices, 2012, 59(10): 2635.

[18]

Solomon P M, Jopling J, Frank D J. Universal tunneling behavior in technologically relevant P/N junction diodes[J]. J Appl Phys, 2004, 95(10): 5800.

[19]

Vishnoi R, Kumar M J. Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport[J]. IEEE Trans Electron Devices, 2014, 61(6): 1936.

[20]

Wu Chunlei, Huang Ru, Huang Qianqian. An analytical surface potential model accounting for the dual-modulation effects in tunnel FETs[J]. IEEE Trans Electron Devices, 2014, 61(8): 2690.

[1]

Bardon M G, Neves H P, Puers R. Pseudo-two-dimensional model for double-gate tunnel FETs considering the junctions depletion regions[J]. IEEE Trans Electron Devices, 2010, 57(4): 827.

[2]

Nagavarapu V, Jhaveri R, Woo J C S. The tunnel source (PNPN) n-MOSFET: a novel high performance transistor[J]. IEEE Trans Electron Devices, 2008, 55(4): 1013.

[3]

Jhaveri R, Nagavarapu V, Woo J C S. Effect of pocket doping and annealing schemes on the source-pocket tunnel field-effect transistor[J]. IEEE Trans Electron Devices, 2011, 58(1): 80.

[4]

Kazazis D, Jannaty P, Zaslavsky A. Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator[J]. Appl Phys Lett, 2009, 94(26): 263508.

[5]

Nayfeh O M, Hoyt J L, Antoniadis D. Strained-Si1-xGex/Si band-to-band tunneling transistors: impact of tunnel-junction germanium composition and doping concentration on switching behavior[J]. IEEE Trans Electron Devices, 2009, 56(10): 2264.

[6]

Kartik G, Youngki Y, Sayeef S. Analysis of InAs vertical and lateral band-to-band tunneling transistors: leveraging vertical tunneling for improved performance[J]. Appl Phys Lett, 2010, 97(3): 033504.

[7]

Ford A C, Yeung C W, Chuang S. Ultrathin body InAs tunneling field-effect transistors on Si substrates[J]. Appl Phys Lett, 2011, 98(11): 113105.

[8]

Chen Y, Zhao J M, Han D D. Extraction of equivalent oxide thickness for HfO2 high k gate dielectric[J]. Chinese Journal of Semiconductors, 2006, 27(5): 852.

[9]

Verhulst A S, Sorée B, Leonelli D. Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor[J]. J Appl Phys, 2010, 107: 024518.

[10]

Wan J, Royer C L, Zaslavsky A. A tunneling field effect transistor model combining interband tunneling with channel transport[J]. J Appl Phys, 2011, 110: 104503.

[11]

Gholizadeh M, Hosseini S E. A 2-D analytical model for double-gate tunnel FETs[J]. IEEE Trans Electron Devices, 2014, 61(5): 1494.

[12]

Xie Q, Xu J, Taur Y. Review and critique of analytic models of MOSFET short-channel effects in subthreshold[J]. IEEE Trans Electron Devices, 2012, 59(6): 1569.

[13]

Lee M J, Choi W Y. Analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs)[J]. Solid-State Electron, 2011, 63: 110.

[14]

Kane E O. Zener tunneling in semiconductors[J]. J Phys Chem Solids, 1959, 12(2): 181.

[15]

ALTAS Device Simulation Software, Silvaco Int. , Santa Clara, CA, USA, Version 5[J]. .

[16]

Wan J, Royer C L, Zaslavsky A. Tunneling FETs on SOI: suppression of ambipolar leakage, low-frequency noise behavior, and modeling[J]. Solid-State Electron, 2011, 65.

[17]

Bhushan B, Nayak K, Rao V R. DC compact model for SOI tunnel field-effect transistors[J]. IEEE Trans Electron Devices, 2012, 59(10): 2635.

[18]

Solomon P M, Jopling J, Frank D J. Universal tunneling behavior in technologically relevant P/N junction diodes[J]. J Appl Phys, 2004, 95(10): 5800.

[19]

Vishnoi R, Kumar M J. Compact analytical model of dual material gate tunneling field-effect transistor using interband tunneling and channel transport[J]. IEEE Trans Electron Devices, 2014, 61(6): 1936.

[20]

Wu Chunlei, Huang Ru, Huang Qianqian. An analytical surface potential model accounting for the dual-modulation effects in tunnel FETs[J]. IEEE Trans Electron Devices, 2014, 61(8): 2690.

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H F Xu, Y H Dai, N Li, J B Xu. A 2-D semi-analytical model of double-gate tunnel field-effect transistor[J]. J. Semicond., 2015, 36(5): 054002. doi: 10.1088/1674-4926/36/5/054002.

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Manuscript received: 22 September 2014 Manuscript revised: Online: Published: 01 May 2015

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