J. Semicond. > Volume 36 > Issue 5 > Article Number: 055009

A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators

Jixuan Xiang , Chixiao Chen , Fan Ye , Jun Xu , , Ning Li and Junyan Ren

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Abstract: This paper presents a 6-b successive approximation register (SAR) ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of distributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to-noise plus distortion ratio (SNDR) is 32.13 dB and the spurious-free dynamic range (SFDR) is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step.

Key words: SAR ADChigh speed2-b/stagenew switching procedureself-locking

Abstract: This paper presents a 6-b successive approximation register (SAR) ADC at the sampling rate of 600 MHz in a 65 nm CMOS process. To pursue high speed, this design employs the idea of the 2-b/stage. Based on this, the proposed structure with a new switching procedure is presented. Compared with traditional structures, it optimizes problems cause by mismatches of DACs and saves power. In addition, this paper takes advantage of distributed comparator topology to improve the speed, while the proposed structure and self-locking technique lighten the kickback and offset caused by multiple comparators. The measurement results demonstrate that the signal-to-noise plus distortion ratio (SNDR) is 32.13 dB and the spurious-free dynamic range (SFDR) is 44.05 dB at 600 MS/s with 5.6 MHz input. By contrast, the SNDR/SFDR respectively drops to 28.46/39.20 dB with Nyquist input. Fabricated in a TSMC 65 nm process, the SAR ADC core occupies an area of 0.045 mm2 and consumes power of 5.01 mW on a supply voltage of 1.2 V resulting in a figure of merit of 252 fJ/conversion-step.

Key words: SAR ADChigh speed2-b/stagenew switching procedureself-locking



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[1]

Ma J X, Sin S W, Seng-Pan U. A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications[J]. IEEE International Symposium on Circuits and Systems, 2006-4305.

[2]

Varzaghani A, Kasapi A, Loizos D N. A 10.3-GS/s, 6-bit flash ADC for 10G Ethernet applications[J]. IEEE J Solid-State Circuits, 2013, 48(12): 3038.

[3]

Chen S W M, Brodersen R W. A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μ m CMOS[J]. IEEE J Solid-State Circuits, 2004, 41(12): 2669.

[4]

Van der Plas G, Verbruggen B. A 150 MS/s 133 W 7 bit ADC in 90 nm digital CMOS[J]. IEEE J Solid-State Circuits, 2008, 43(12): 2631.

[5]

Wong S S, Chio U F, Chan C H. A 4.8-bit ENOB 5-bit 500 MS/s binary-search ADC with minimized number of comparators[J]. IEEE Asian Solid State Circuits Conference (A-SSCC), 2011-73.

[6]

Lin Y Z, Liu C C, Huang G Y. A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS[J]. IEEE Trans Circuits Syst I: Regular Papers, 2013, 60(3): 570.

[7]

Wei H, Chan C H, Chio U F. An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC[J]. IEEE J Solid-State Circuits, 2012, 47(11): 2763.

[8]

Lien Y C. 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology[J]. Symposium on VLSI Circuits (VLSIC), 2012-88.

[9]

Hong H K, Kim W, Park S J. A 7 b 1 GS/s 7.2 mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control[J]. IEEE Custom Integrated Circuits Conference (CICC), 2012-1.

[10]

Cao Z, Yan S, Li Y. A 32 mW 1.25 GS/s 6 b 2 b/Step SAR ADC in 0.13 μ m CMOS[J]. IEEE J Solid-State Circuits, 2009, 44(3): 862.

[11]

Ginsburg B P, Chandrakasan A. 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC[J]. IEEE J Solid-State Circuits, 2007, 42(4): 739.

[12]

Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731.

[13]

Jiang T, Liu W, Zhong F Y. A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS[J]. IEEE J Solid-State Circuits, 2012, 47(10): 2444.

[14]

Yang J, Naing T L, Brodersen B. A 1-GS/s 6-bit 6.7-mW ADC in 65-nm CMOS[J]. IEEE Custom Integrated Circuits Conference, 2009-287.

[15]

Han Xue, Wei Qi, Yang Huazhong. A single channel, 6-bit 230-MS/s asynchronous SAR ADC based on 2 bits/stage[J]. Journal of Semiconductors, 2014, 35(7): 075005.

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J X Xiang, C X Chen, F Ye, J Xu, N Li, J Y Ren. A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and self-locking comparators[J]. J. Semicond., 2015, 36(5): 055009. doi: 10.1088/1674-4926/36/5/055009.

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Manuscript received: 23 September 2014 Manuscript revised: Online: Published: 01 May 2015

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