Propagation delay and power dissipation for different aspect ratio of single-walled carbon nanotube bundled TSV

Tanu Goyal; Manoj Kumar Majumder; Brajesh Kumar Kaushik

doi:10.1088/1674-4926/36/6/065001

Abstract: Through-silicon vias (TSVs) have provided an attractive solution for three-dimensional (3D) integrated devices and circuit technologies with reduced parasitic losses and power dissipation, higher input-output (I/O) density and improved system performance. This paper investigates the propagation delay and average power dissipation of single-walled carbon nanotube bundled TSVs having different via radius and height. Depending on the physical configuration, a comprehensive and accurate analytical model of CNT bundled TSV is employed to represent the via (vertical interconnect access) line of a driver-TSV-load (DTL) system. The via radius and height are used to estimate the bundle aspect ratio (AR) and the cross-sectional area. For a fixed via height, the delay and the power dissipation are reduced up to 96.2% using a SWCNT bundled TSV with AR = 300 : 1 in comparison to AR = 6 : 1.

Key words: carbon nanotube, through-silicon vias, equivalent RLC circuit model, propagation delay, power-delay product, area-delay product

References:

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[2]	Banerjee K, Souri S J, Kapur P. 3-D ICs: a novel chip design for improving deep-sub micrometer interconnect performance and systems-on-chip integration[J]. Proc IEEE, 2001, 89(5): 602.
[3]	Kumari A, Majumder M K, Kaushik B K. Effect of polymer liners in CNT based through silicon vias[J]. Proceedings IEEE Electronics Components and Technology Conference (ECTC), 2014: 1921.
[4]	Lu J Q. 3-D hyperintegration and packaging technologies for micro-nano systems[J]. Proc IEEE, 2009, 97(1): 18.
[5]	Knickerbocker J U, Andry P S, Colgan E. 2.5D and 3D technology challenges and test vehicle demonstrations[J]. Proceedings of IEEE 62nd International Conference on Electronic Components and Technology Conference (ECTC), 2012-1068.
[6]	Kaushik B K, Majumder M K, Kumar V R. Carbon nanotube based 3-D interconnects-a reality or a distant dream[J]. IEEE Circuits Syst Mag, 2014, 14(4): 16.
[7]	Kumar V R, Majumder M K, Kaushik B K. Graphene based on-chip interconnects and TSVs-prospects and challenges[J]. IEEE Nanotechnol Mag, 2014, 8(4): 14.
[8]	Davis W R, Wilson J, Mick S. Demystifying 3D ICs: the pros and cons of going vertical[J]. IEEE Design and Test of Computers, 2005, 22(6): 498.
[9]	Christie P, Stroobandt D. The interpretation and application of Rent's rule[J]. IEEE Trans VLSI Syst, 2000, 8(6): 1.
[10]	Naeemi A, Sarvari R, Meindl J D. Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)[J]. IEEE Electron Device Lett, 2005, 26(2): 84.
[11]	Li H, Xu C, Srivastava N. Carbon nanomaterials for next-generation interconnects and passives: physics, status, and prospects[J]. IEEE Trans Electron Devices, 2009, 56(9): 1799.
[12]	Hoenlein W, Kreupl F, Duesberg G S. Carbon nanotube applications in microelectronics[J]. IEEE Trans Compon Packag Technolog, 2004, 27(4): 629.
[13]	Saito R, Dresselhaus G, Dresselhaus S. Physical properties of carbon nanotubes[J]. London, UK: Imperial College Press, 1998.
[14]	Wei Zhen, Li Xiaochun, Mao Junfa. An accurate RLGC circuit model for dual tapered TSV structure[J]. Journal of Semiconductors, 2014, 35(9): 095008.
[15]	Wu Heng, Tang Zhen'an, Wang Zhu. Simulation of through via bottom-up copper plating with accelerator for the filling of TSVs[J]. Journal of Semiconductors, 2013, 34(9): 096001.
[16]	Leung L L W, Chen K J. Microwave characterization and modeling of high aspect ratio through-wafer interconnect vias in silicon substrates[J]. IEEE Trans Microw Theory Tech, 2005, 53(8): 2472.
[17]	Li H, Banerjee K. High-frequency analysis of carbon nanotube interconnects and implications for on-chip inductor design[J]. IEEE Trans Electron Devices, 2009, 56(10): 2202.
[18]	Pu S N, Yin W Y, Mao J F. Crosstalk prediction of single-and double-walled carbon nanotube (SWCNT/ DWCNT) bundle interconnects[J]. IEEE Trans Electron Devices, 2009, 56(4): 560.
[19]	Xu C, Li H, Suaya R. Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs[J]. IEEE Trans Electron Devices, 2010, 57(12): 3405.
[20]	Burke P J. Lüttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes[J]. IEEE Trans Nanotechnol, 2010, 1(3): 129.
[21]	Andriotis A N, Menon M, Froudakis G E. Various bonding configurations of transition-metal atoms on carbon nanotubes: Their effect on contact resistance[J]. Appl Phys Lett, 2000, 76(26): 3890.
[22]	Majumder M K, Kaushik B K, Manhas S K. Analysis of delay and dynamic crosstalk in bundled carbon nanotube interconnects[J]. IEEE Trans Electromagnetic Compatibility, 2014.
[23]	Sarto M S, Tamburrano A. Single-conductor transmission-line model of multiwall carbon nanotubes[J]. IEEE Trans Nanotechnol, 2010, 9(1): 82.
[24]	Li H, Yin W Y, Banerjee K. Circuit modeling and performance analysis of multi-walled carbon nanotube interconnects[J]. IEEE Trans Electron Devices, 2008, 55(6): 1328.
[25]	Zhao W S, Yin W Y, Guo Y X. Electromagnetic compatibility-oriented study on through silicon single-walled carbon nanotube bundle via (TS-SWCNTBV) arrays[J]. IEEE Trans Electromagnetic Compatibility, 2012, 54(1): 149.

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Propagation delay and power dissipation for different aspect ratio of single-walled carbon nanotube bundled TSV

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