J. Semicond. > Volume 36 > Issue 6 > Article Number: 065006

A high speed direct digital frequency synthesizer based on multi-channel structure

Ling Yuan , , Qiang Zhang and Yin Shi

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Abstract: This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 × 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.

Key words: direct digital frequency synthesizer (DDFS)multi-channelphase-to-sine-amplitude converters (PSAC)

Abstract: This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 × 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.

Key words: direct digital frequency synthesizer (DDFS)multi-channelphase-to-sine-amplitude converters (PSAC)



References:

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[1]

Sodagar A M, Lahiji G R. Mapping from phase to sine-amplitude in direct digital frequency synthesizers using parabolic approximation[J]. IEEE Trans Circuits Syst II, 2000, 47: 1452.

[2]

Mortezapour S, Lee E K F. Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter[J]. IEEE J Solid-State Circuits, 1999, 34: 1350.

[3]

Jiang J, Lee E K F. A low-power segmented nonlinear DAC-based direct digital frequency synthesizer[J]. IEEE J Solid-State Circuits, 2002, 37: 1326.

[4]

Van der Plas G A M, Vandenbussche J, Sansen W. A 14-bit intrinsic accuracy Q2 random walk CMOS DAC[J]. IEEE J Solid-State Circuits, 1999, 34: 1708.

[5]

Yuan L, Ni W, Shi Y. A 10-bit 2 GHz current-steering CMOS D/A converter[J]. IEEE Int Symp Circuits Syst (ISCAS), 2007.

[6]

Hao Zhikun, Zhang Qiang, Ni Weining. A high-performance MUX-direct digital frequency synthesizer with quarter ROMs[J]. Journal of Semiconductors, 2012, 33: 015008.

[7]

D'Souza S, Hsiao F, Tang A. A 10-bit 2-GS/s DAC-DDFS-IQ-controller baseband enabling a self-healing 60-GHz radio-on-chip[J]. IEEE Trans Circuits Syst II, 2013, 60: 457.

[8]

Yoo T, Jung Y H, Yeoh H C. 21.3 A 2 GHz 130 mW direct-digital frequency synthesizer with a nonlinear DAC in 55 nm CMOS[J]. IEEE International Solid-State Circuits Conference, Digest of Technical Papers (ISSCC),, 2014: 364.

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L Yuan, Q Zhang, Y Shi. A high speed direct digital frequency synthesizer based on multi-channel structure[J]. J. Semicond., 2015, 36(6): 065006. doi: 10.1088/1674-4926/36/6/065006.

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Manuscript received: 02 November 2014 Manuscript revised: Online: Published: 01 June 2015

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