J. Semicond. > Volume 37 > Issue 3 > Article Number: 035001

High performance 14-bit pipelined redundant signed digit ADC

Swina Narula and Sujata Pandey

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Abstract: A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.

Key words: pipelined ADCMDACnon-ideal errorssignal to noise ratio(SNR)spurious free dynamic range(SFDR)signal to noise plus distortion(SNDR)

Abstract: A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.

Key words: pipelined ADCMDACnon-ideal errorssignal to noise ratio(SNR)spurious free dynamic range(SFDR)signal to noise plus distortion(SNDR)



References:

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Wen W H, Qiao M. Behavioral modeling of a 12-bit 500-MS/s multi-stage ADC[J]. PIERS Proceedings, Taipei, 2013.

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Yoo S M, Park J B, Lee S H. A 2.5-V 120-M sample/s CMOS pipelined ADC based on merged-capacitor switching[J]. IEEE Trans Circuits Syst, 2004, 51(5): 269.

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Gustavsson M, Wikner J J, Tan N N. CMOS data converters for communications[J]. Kluwer Academic Publishers, 2000.

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Lin J F, Chang S J, Kung T C. Transition code based linearity test method for pipelined ADCs with digital correction logic[J]. IEEE Trans Very Large Scale Integration System, 2011, 19(12): 2158.

[7]

Bilhan E, Estrada P C. Behavioral model of pipeline ADC by using Simulink[J]. South-west Symposium on Mixed-signal Design, 2001: 147.

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Malcovati P, Brigati S, Francesconi F. Behavioral modeling of switched-capacitor sigma-delta modulators[J]. IEEE Trans Circuits Syst, 2003, 50(3): 352.

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Phillp E A, Holberg D R. CMOS analog circuit design[J]. Beijing:Publishing House of Electronic Industry, 2007.

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Moon U K, Song B S. Background digital calibration techniques for pipelined ADCs[J]. IEEE Trans Circuits Syst Ⅱ, 1997, 44(2): 102.

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Peruzzi R O. Verification of digitally calibrated analog systems with Verilog-AMS behavioral models[J]. IEEE Behavioral modeling and Simulation Conference, 2006.

[12]

Diaz-Madrid J A, Domenech-Asensi , Lopez-Alcantud G. VHDL-AMD model of a 40 M/s 13 bits pipeline ADC[J]. Mixed Design of Integrated Circuits and System, MIXDES, 2006: 555.

[13]

Peralías E, Rueda A, Prieto J A. DFT & on-line test of high-performance data converters:a practical case[J]. Proc International Test Conference, Washington, USA, 1998: 534.

[14]

Acosta A J, Peralías E, Rueda A. A VHDL behavioral model for pipeline ADCs[J]. Proc International Workshop on ADC Modelling and Testing, Bordeaux, France, 1999: 35.

[15]

Dumlugol D, Webber D. Analog modeling using event driven HDL's[J]. Proc International Conference on VLSI Design, 1994: 53.

[16]

Ahmed I, Muldar J, Johns D A. A low power capacitive charge pump based pipelined ADC[J]. IEEE J Solid-State circuits, 2010, 45(5): 1016.

[17]

Gharbiya A, Caldwell T C, Johns D A. High speed oversampling analog-to-digital converters[J]. International Journal of High Speed Electronics and Systems, 2005, 15(2): 297.

[18]

Barra S, Kouda S, Dendouga A. Simulink behavioral modeling of a 10-bit pipelined ADC[J]. International Journal of Automation and Computing, 2013, 10(2): 134.

[19]

Lin J F, Chang S J, Liu C C. A 10-bit 60 MS/s low power pipelined ADC with split capacitor CDS technique[J]. IEEE Trans Circuits Syst, 2010, 57(3): 163.

[20]

Tangel A, Choi K. The CMOS inverter as comparator in ADC designs[J]. Analog Integrated Circuits and Signal Processing, 2004, 39(2): 147.

[21]

Hor H C, Siek L. Review of VCO based ADC in modern deep submicron CMOS technology[J]. IEEE International Symposium on Radio Frequency Integration Technology, 2012: 86.

[22]

Li G, Tousi Y M, Hassibi A. Delay line based analog to digital converters[J]. IEEE Trans Circuit Syst Ⅱ-Express Briefs, 2009, 56: 464.

[23]

Verma A, Razavi B. A 10-bit 500 MS/s 55 mW CMOS ADC[J]. IEEE J Solid-State Circuits, 2009, 44(11): 3039.

[24]

Hanfoug S, Moulahcene F, Bouguechal N E. Contribution to the modeling and simulation of current mode pipeline ADC based on Matlab[J]. International Journal of Hybrid Information Technology, 2015, 8(3): 83.

[25]

Lee S C, Jeon Y D, Kim K D. A 10b 205 MS/s 1 mm2 90 nm pipeline ADC for flat panel display application[J]. IEEE ISSCC Dig Tech papers, 2007: 458.

[1]

Peralias, Acosta, Rueda. A VHDL-based methodology for the design and verification of pipeline A/D converters[J]. Design, Automation and Test in Europe Conference and Exhibition, 2000: 534.

[2]

Wen W H, Qiao M. Behavioral modeling of a 12-bit 500-MS/s multi-stage ADC[J]. PIERS Proceedings, Taipei, 2013.

[3]

Maloberti F, Estrada P, Valero A. Behavioral modeling and simulation of data converters[J]. IMEKO, Viena, Austria, 2000.

[4]

Yoo S M, Park J B, Lee S H. A 2.5-V 120-M sample/s CMOS pipelined ADC based on merged-capacitor switching[J]. IEEE Trans Circuits Syst, 2004, 51(5): 269.

[5]

Gustavsson M, Wikner J J, Tan N N. CMOS data converters for communications[J]. Kluwer Academic Publishers, 2000.

[6]

Lin J F, Chang S J, Kung T C. Transition code based linearity test method for pipelined ADCs with digital correction logic[J]. IEEE Trans Very Large Scale Integration System, 2011, 19(12): 2158.

[7]

Bilhan E, Estrada P C. Behavioral model of pipeline ADC by using Simulink[J]. South-west Symposium on Mixed-signal Design, 2001: 147.

[8]

Malcovati P, Brigati S, Francesconi F. Behavioral modeling of switched-capacitor sigma-delta modulators[J]. IEEE Trans Circuits Syst, 2003, 50(3): 352.

[9]

Phillp E A, Holberg D R. CMOS analog circuit design[J]. Beijing:Publishing House of Electronic Industry, 2007.

[10]

Moon U K, Song B S. Background digital calibration techniques for pipelined ADCs[J]. IEEE Trans Circuits Syst Ⅱ, 1997, 44(2): 102.

[11]

Peruzzi R O. Verification of digitally calibrated analog systems with Verilog-AMS behavioral models[J]. IEEE Behavioral modeling and Simulation Conference, 2006.

[12]

Diaz-Madrid J A, Domenech-Asensi , Lopez-Alcantud G. VHDL-AMD model of a 40 M/s 13 bits pipeline ADC[J]. Mixed Design of Integrated Circuits and System, MIXDES, 2006: 555.

[13]

Peralías E, Rueda A, Prieto J A. DFT & on-line test of high-performance data converters:a practical case[J]. Proc International Test Conference, Washington, USA, 1998: 534.

[14]

Acosta A J, Peralías E, Rueda A. A VHDL behavioral model for pipeline ADCs[J]. Proc International Workshop on ADC Modelling and Testing, Bordeaux, France, 1999: 35.

[15]

Dumlugol D, Webber D. Analog modeling using event driven HDL's[J]. Proc International Conference on VLSI Design, 1994: 53.

[16]

Ahmed I, Muldar J, Johns D A. A low power capacitive charge pump based pipelined ADC[J]. IEEE J Solid-State circuits, 2010, 45(5): 1016.

[17]

Gharbiya A, Caldwell T C, Johns D A. High speed oversampling analog-to-digital converters[J]. International Journal of High Speed Electronics and Systems, 2005, 15(2): 297.

[18]

Barra S, Kouda S, Dendouga A. Simulink behavioral modeling of a 10-bit pipelined ADC[J]. International Journal of Automation and Computing, 2013, 10(2): 134.

[19]

Lin J F, Chang S J, Liu C C. A 10-bit 60 MS/s low power pipelined ADC with split capacitor CDS technique[J]. IEEE Trans Circuits Syst, 2010, 57(3): 163.

[20]

Tangel A, Choi K. The CMOS inverter as comparator in ADC designs[J]. Analog Integrated Circuits and Signal Processing, 2004, 39(2): 147.

[21]

Hor H C, Siek L. Review of VCO based ADC in modern deep submicron CMOS technology[J]. IEEE International Symposium on Radio Frequency Integration Technology, 2012: 86.

[22]

Li G, Tousi Y M, Hassibi A. Delay line based analog to digital converters[J]. IEEE Trans Circuit Syst Ⅱ-Express Briefs, 2009, 56: 464.

[23]

Verma A, Razavi B. A 10-bit 500 MS/s 55 mW CMOS ADC[J]. IEEE J Solid-State Circuits, 2009, 44(11): 3039.

[24]

Hanfoug S, Moulahcene F, Bouguechal N E. Contribution to the modeling and simulation of current mode pipeline ADC based on Matlab[J]. International Journal of Hybrid Information Technology, 2015, 8(3): 83.

[25]

Lee S C, Jeon Y D, Kim K D. A 10b 205 MS/s 1 mm2 90 nm pipeline ADC for flat panel display application[J]. IEEE ISSCC Dig Tech papers, 2007: 458.

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S Narula, Sujata Pandey. High performance 14-bit pipelined redundant signed digit ADC[J]. J. Semicond., 2016, 37(3): 035001. doi: 10.1088/1674-4926/37/3/035001.

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Manuscript received: 12 July 2015 Manuscript revised: Online: Published: 01 March 2016

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