J. Semicond. > Volume 37 > Issue 3 > Article Number: 035003

A 430 mW 16 b 170 MS/s CMOS pipelined ADC with 77.2 dB SNR and 97.6 dB SFDR

Hui Zhang , , Dan Li , Lei Wan , Hui Zhang , Haijun Wang , Yuan Gao , Feili Zhu , Ziqi Wang and Xuexin Ding

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Abstract: A 16-bit 170 MS/s pipelined ADC implemented in 0.18μm CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarged full scale range makes it possible to obtain a high SNR with smaller sampling capacitors, thus achieving higher speed and low power. This ADC attains an SNR of 77.2 dBFS, an SFDR of 97.6 dBc for a 10 MHz input signal, while preserving an SFDR>80 dBc up to 300 MHz input frequency. The ADC consumes 430 mW from a 1.8 V supply and occupies a 17 mm2 active area.

Key words: pipelined ADCcalibrationSHA-lessIF sampling

Abstract: A 16-bit 170 MS/s pipelined ADC implemented in 0.18μm CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarged full scale range makes it possible to obtain a high SNR with smaller sampling capacitors, thus achieving higher speed and low power. This ADC attains an SNR of 77.2 dBFS, an SFDR of 97.6 dBc for a 10 MHz input signal, while preserving an SFDR>80 dBc up to 300 MHz input frequency. The ADC consumes 430 mW from a 1.8 V supply and occupies a 17 mm2 active area.

Key words: pipelined ADCcalibrationSHA-lessIF sampling



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[1]

Ali A, Morgan A, Dillon C. A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration[J]. IEEE ISSCC Dig Tech Papers, 2010: 292.

[2]

Devarajan S, Singer L, Kelly D. A 16 b 125 MS/s 385 mW 78.7 dB SNR CMOS pipelined ADC[J]. IEEE ISSCC Dig Tech Papers, 2009: 86.

[3]

Payne R, Coris M, Smith D. A 16b 100-to-160 MS/s SiGe BiCMOS pipelined ADC with 100 dBFS SFDR[J]. IEEE ISSCC Dig Tech Papers, 2010: 294.

[4]

Murmann B. ADC performance survey 1997-2015[J]. .

[5]

Abo A M, Gray P R. A 1.5-V, 10-bit, 14.3 MS/s CMOS pipeline analog-to-digital converter[J]. IEEE J Solid-State Circuits, 1999, 34: 599.

[6]

Hans V D V, Buter B A J, Hendrik V D P. A 1.2-V 250-mW 14-b 100-MS/s digitally calibrated pipelined ADC in 90-nm CMOS[J]. IEEE J Solid-State Circuits, 2009, 44: 1047.

[7]

Razavi B. Design of analog CMOS integrated circuits[J]. McGraw-Hill Company, 2001: 309.

[8]

Bardsley S, Dillon C, Kummaraguntla R. A 100-dB SFDR 80-MSPS 14-bit 0.35μm BiCMOS pipelined ADC[J]. IEEE J Solid-State Circuits, 2006, 41: 2144.

[9]

Ali A A, Dillon C, Sneed R. A 14-bit 125MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter[J]. IEEE J Solid-State Circuits, 2006, 41: 1846.

[10]

Chang D Y. Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier[J]. IEEE Trans Circuits Syst I Regular Papers, 2004, 51: 2123.

[11]

Brown T W, Hakkarainen M, Fiez T S. Frequency dependent sampling linearity[J]. IEEE Trans Circuits Syst I, Regular Papers, 2009, 56: 740.

[12]

Yu H. A 12b 50MSPS 34mW pipelined ADC[J]. IEEE CICC Dig Tech Papers, 2008: 297.

[13]

Karanicolas A N, Lee H S, Bacrania K L. A 15-b 1-Msample/s digitally self-calibrated pipeline ADC[J]. IEEE J Solid-State Circuits, 1993, 28: 1207.

[14]

Agilent Technologies. Agilent E8663D PSG RF analog signal generator datasheet[J]. , 2012.

[15]

Kester W. MT-008:converting oscillator phase noise to time jitter[J]. Analog Devices, 2010.

[16]

Brunsilius J, Siragusa E, Kosi S. A 16b 80 MS/s 100 mW 77.6 dB SNR CMOS pipelined ADC[J]. IEEE ISSCC Dig Tech Papers, 2011: 186.

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H Zhang, D Li, L Wan, H Zhang, H J Wang, Y Gao, F L Zhu, Z Q Wang, X X Ding. A 430 mW 16 b 170 MS/s CMOS pipelined ADC with 77.2 dB SNR and 97.6 dB SFDR[J]. J. Semicond., 2016, 37(3): 035003. doi: 10.1088/1674-4926/37/3/035003.

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Manuscript received: 14 July 2015 Manuscript revised: Online: Published: 01 March 2016

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