J. Semicond. > Volume 37 > Issue 5 > Article Number: 055003

A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array

Jingjing Wang , Zemin Feng , Rongjin Xu , Chixiao Chen , Fan Ye , Jun Xu , and Junyan Ren

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Abstract: A low power 9 bit 100 MS/s successive approximation register analog-to-digital converter (SAR ADC) with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits (ENOB) of 7.4 bit, a signal-to-noise plus distortion ratio (SNDR) of 46.40 dB and a spurious-free dynamic range (SFDR) of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit (FOM) of the SAR ADC achieves 23.75 fJ/conv.

Key words: SAR ADClow powercustom metal-oxide-metal capacitorcapacitor array structure

Abstract: A low power 9 bit 100 MS/s successive approximation register analog-to-digital converter (SAR ADC) with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits (ENOB) of 7.4 bit, a signal-to-noise plus distortion ratio (SNDR) of 46.40 dB and a spurious-free dynamic range (SFDR) of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit (FOM) of the SAR ADC achieves 23.75 fJ/conv.

Key words: SAR ADClow powercustom metal-oxide-metal capacitorcapacitor array structure



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Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731.

[2]

Chen Chixiao, Xiang Jixuan, Chen Huabin. A capacitive DAC with custom 3-D 1-fF MOM unit capacitors optimized for fast-settling routing in high speed SAR ADCs[J]. Journal of Semiconductors, 2015, 36(5): 055011.

[3]

Liu W, Huang P, Chiu Y. A 12 b 22.5/45 MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR[J]. Digest of Technical Papers of IEEE International Solid-State Circuits Conference (ISSCC), 2010: 380.

[4]

Morie T, Miki T, Matsukawa K. A 71dB-SNDR 50 MS/s 4.2 mW CMOS SAR ADC by SNR enhancement techniques utilizing noise[J]. Digest of Technical Papers of IEEE International Solid-State Circuits Conference (ISSCC), 2013: 272.

[5]

Hong H K, Kang H W, Sung B. An 8.6 ENOB 900 MS/s time-interleaved 2 b/cycle SAR ADC with a 1 b/cycle reconfiguration for resolution enhancement[J]. Digest of Technical Papers of IEEE International Solid-State Circuits Conference (ISSCC), 2013: 470.

[6]

Chen Huabin, Xiang Jixuan, Xue Xiangyan. An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system. Journal of Semiconductors[J]. , 2014, 35(11): 115008.

[7]

Xiang Jixuan, Chen Chixiao, Ye Fan. A 6-b 600 MS/s SAR ADC with a new switching procedure of 2-b/stage and selflocking comparators[J]. Journal of Semiconductors, 2015, 36(5): 055009.

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J J Wang, Z M Feng, R J Xu, C X Chen, F Ye, J Xu, J Y Ren. A 100 MS/s 9 bit 0.43 mW SAR ADC with custom capacitor array[J]. J. Semicond., 2016, 37(5): 055003. doi: 10.1088/1674-4926/37/5/055003.

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History

Manuscript received: 17 August 2015 Manuscript revised: Online: Published: 01 May 2016

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