J. Semicond. > Volume 37 > Issue 7 > Article Number: 075001

A high efficiency all-PMOS charge pump for 3D NAND flash memory

Liyin Fu , Yu Wang , , Qi Wang and Zongliang Huo ,

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Abstract: For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.

Key words: charge pump circuithigh power efficiencyperipheral circuit design3D vertical NAND flash memory

Abstract: For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.

Key words: charge pump circuithigh power efficiencyperipheral circuit design3D vertical NAND flash memory



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Chi Yuan, Lai Xinquan, Du Hanxiao. Analysis of switch-induced error voltage for automatic conversion mode change charge pumps[J]. Journal of Semiconductors, 2015, 36(5): 055007.

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Liu Faen, Wang Zhigong, Li Zhiqun. Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop[J]. Journal of Semiconductors, 2014, 35(10): 105006.

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Zhang Xiwen, Lee Hoi. Gain-enhanced monolithic charge pump with simultaneous dynamic gate and substrate control[J]. IEEE Trans Very Large Scale Integr Syst, 2013, 21(3): 593.

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Li Xian, Zhong Huicai, Tang Zhenhui. Reliable antifuse one-time-programmable scheme with charge pump for postpackage repair of DRAM[J]. IEEE Trans Very Large Scale Integr Syst, 2015, 23(9): 1956.

[1]

Elliott J, Jung E S. Ushering in the 3D memory era with V-NAND[J]. Flash Memory Summit Special Keynote B, 2013.

[2]

Jang J, Kim H S, Cho W. Vertical cell array using TCAT (terabitcell array transistor) technology for ultrahigh density NAND flash memory[J]. IEEE International Symposium on VLSI Technology, 2009: 192.

[3]

Park K T, Han J, Kim D. Three-dimensional 128 Gb MLC vertical NAND flash memory with 24-WL stacked layers and 50 MB/s high-speed programming[J]. IEEE J Solid-State Circuits, 2015, 50(1): 204.

[4]

Pelliconi R, Iezzi D, Baroni A. Power efficient charge pump in deep submicron standard CMOS technology[J]. IEEE J Solid-State Circuits, 2003, 38(6): 1068.

[5]

Shin J, Chung I Y, Park Y J. A new charge pump without degradation in threshold voltage due to body effect[J]. IEEE J Solid-State Circuits, 2003, 5(8): 1227.

[6]

Richelli A, Colalongo L, Mensi L. Charge pump architectures based on dynamic gate control of the pass transistors[J]. IEEE Trans Very Large Scale Integr Syst, 2009, 7(17): 964.

[7]

Dickson J F. On chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique[J]. IEEE J Solid-State Circuits, 1976, 11(3): 374.

[8]

Palumbo G, Pappalardo D, Gaibotti M. Charge-pump circuits:power-consumption optimization[J]. IEEE Trans Circuits Syst I, 2002, 49(11): 1535.

[9]

Hsu C P, Lin H C. Analytical models of output voltages and power efficiencies for multistage charge pumps[J]. IEEE Trans Power Electron, 2010, 25(6): 1735.

[10]

Chi Yuan, Lai Xinquan, Du Hanxiao. Analysis of switch-induced error voltage for automatic conversion mode change charge pumps[J]. Journal of Semiconductors, 2015, 36(5): 055007.

[11]

Liu Faen, Wang Zhigong, Li Zhiqun. Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop[J]. Journal of Semiconductors, 2014, 35(10): 105006.

[12]

Zhang Xiwen, Lee Hoi. Gain-enhanced monolithic charge pump with simultaneous dynamic gate and substrate control[J]. IEEE Trans Very Large Scale Integr Syst, 2013, 21(3): 593.

[13]

Li Xian, Zhong Huicai, Tang Zhenhui. Reliable antifuse one-time-programmable scheme with charge pump for postpackage repair of DRAM[J]. IEEE Trans Very Large Scale Integr Syst, 2015, 23(9): 1956.

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L Y Fu, Y Wang, Q Wang, Z L Huo. A high efficiency all-PMOS charge pump for 3D NAND flash memory[J]. J. Semicond., 2016, 37(7): 075001. doi: 10.1088/1674-4926/37/7/075001.

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Manuscript received: 23 December 2015 Manuscript revised: Online: Published: 01 July 2016

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