J. Semicond. > Volume 37 > Issue 7 > Article Number: 075005

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

Mingyuan Yu 1, , Ting Li 2, , Jiaqi Yang 1, , Shuangshuang Zhang 1, , Fujiang Lin 1, and Lin He 1, ,

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Abstract: This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μ W at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2.

Key words: SAR ADClow powerhigh speedsubrangemodified SAR logic

Abstract: This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μ W at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2.

Key words: SAR ADClow powerhigh speedsubrangemodified SAR logic



References:

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[2]

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Verma N, Chandrakasan A P. An ultra-low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes[J]. IEEE J Solid-State Circuits, 2007, 42(6): 1196.

[4]

Harpe P J, Zhou C, Bi Y. A 26μ W 8 bit 10 MS/s asynchronous saradc for low energy radios[J]. IEEE J Solid-State Circuits, 2011, 46(7): 1585.

[5]

Brenna S, Bonfanti A, Lacaita A L. A 6-fJ/conversion-step 200-KSps asynchronous SAR ADC with attenuation capacitor in 130-nm CMOS[J]. Analog Integrated Circuits and Signal Processing, 2014, 81(1): 181.

[6]

Liu Wei, Wei Tingcun, Li Bo. A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors[J]. Journal of Semiconductors, 2015, 36(4): 045007.

[7]

Li Yongyuan, Guo Wei, Zhu Zhangming. Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications[J]. Journal of Semiconductors, 2015, 36(4): 045009.

[8]

Han Xue, Wei Qi, Yang Huazhong. A single channel, 6-bit 410-MS/s 3 bits/stage asynchronous SAR ADC based on resistive DAC[J]. Journal of Semiconductors, 2015, 36(5): 055010.

[9]

Ginsburg B P, Chandrakasan A P. 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC[J]. IEEE J Solid-State Circuits, 2007, 42(4): 739.

[10]

Zhu Y, Chan C H, Chio U. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE J Solid-State Circuits, 2010, 45(6): 1111.

[11]

Chen S W M, Brodersen R W. A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS[J]. IEEE J Solid-State Circuits, 2006, 41(12): 2669.

[12]

Jiang T, Liu W, Zhong F Y. A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS[J]. IEEE J Solid-State Circuits, 2012, 47(10): 2444.

[13]

Lin Y Z, Liu C C, Huang G Y. A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS[J]. IEEE Trans Circuits Syst I, 2013, 60(3): 570.

[14]

Wang Ya, Xue Chunying, Li Fule. A low power 11-bit 100 MS/s SAR ADC IP[J]. Journal of Semiconductors, 2015, 36(2): 025003.

[15]

Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731.

[16]

Dessouky M, Kaiser A. Very low-voltage digital-audio Δ Σ modulator with 88-dB dynamic range using local switch bootstrapping[J]. IEEE J Solid-State Circuits, 2001, 36(3): 349.

[17]

Gu Weiru, Ye Fan, Ren Junyan. An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation[J]. Journal of Semiconductors, 2014, 35(8): 085006.

[18]

Ogawa T, Kobayashi H, Hotta M. SAR ADC algorithm with redundancy[J]. IEEE APCCAS, 2008: 268.

[19]

Miyahara M, Asada Y, Paik D. A low-noise self-calibrating dynamic comparator for high-speed ADCs[J]. IEEE ASSCC, 2008: 269.

[20]

Yuan J, Svensson C. High-speed CMOS circuit technique[J]. IEEE J Solid-State Circuits, 1989, 24(1): 62.

[21]

Harikumar P, Wikner J J. A 10-bit 50MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer[J]. Integration, the VLSI Journal, 2015, 50: 28.

[22]

ChoS H, Lee C K, Kwon J K. A 550-μ W 10-b 40-MS/s SAR ADC with multistep addition-only digital error correction[J]. IEEE J Solid-State Circuits, 2011, 46(8): 1881.

[1]

Pang W Y, Wang C S, Chang Y K, et al. A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications. IEEE A-SSCC, 2009:149

[2]

Zhang D, Bhide A, Alvandpour A. A 53-nW 9.1-ENOB 1-KS/s SAR ADC in 0.13-μm CMOS for medical implant devices[J]. IEEE J Solid-State Circuits, 2012, 47(7): 1585.

[3]

Verma N, Chandrakasan A P. An ultra-low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes[J]. IEEE J Solid-State Circuits, 2007, 42(6): 1196.

[4]

Harpe P J, Zhou C, Bi Y. A 26μ W 8 bit 10 MS/s asynchronous saradc for low energy radios[J]. IEEE J Solid-State Circuits, 2011, 46(7): 1585.

[5]

Brenna S, Bonfanti A, Lacaita A L. A 6-fJ/conversion-step 200-KSps asynchronous SAR ADC with attenuation capacitor in 130-nm CMOS[J]. Analog Integrated Circuits and Signal Processing, 2014, 81(1): 181.

[6]

Liu Wei, Wei Tingcun, Li Bo. A 12-bit 1 MS/s SAR-ADC for multi-channel CdZnTe detectors[J]. Journal of Semiconductors, 2015, 36(4): 045007.

[7]

Li Yongyuan, Guo Wei, Zhu Zhangming. Design of a low power 10 bit 300 ksps multi-channel SAR ADC for wireless sensor network applications[J]. Journal of Semiconductors, 2015, 36(4): 045009.

[8]

Han Xue, Wei Qi, Yang Huazhong. A single channel, 6-bit 410-MS/s 3 bits/stage asynchronous SAR ADC based on resistive DAC[J]. Journal of Semiconductors, 2015, 36(5): 055010.

[9]

Ginsburg B P, Chandrakasan A P. 500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC[J]. IEEE J Solid-State Circuits, 2007, 42(4): 739.

[10]

Zhu Y, Chan C H, Chio U. A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J]. IEEE J Solid-State Circuits, 2010, 45(6): 1111.

[11]

Chen S W M, Brodersen R W. A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-μm CMOS[J]. IEEE J Solid-State Circuits, 2006, 41(12): 2669.

[12]

Jiang T, Liu W, Zhong F Y. A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS[J]. IEEE J Solid-State Circuits, 2012, 47(10): 2444.

[13]

Lin Y Z, Liu C C, Huang G Y. A 9-bit 150-MS/s subrange ADC based on SAR architecture in 90-nm CMOS[J]. IEEE Trans Circuits Syst I, 2013, 60(3): 570.

[14]

Wang Ya, Xue Chunying, Li Fule. A low power 11-bit 100 MS/s SAR ADC IP[J]. Journal of Semiconductors, 2015, 36(2): 025003.

[15]

Liu C C, Chang S J, Huang G Y. A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J]. IEEE J Solid-State Circuits, 2010, 45(4): 731.

[16]

Dessouky M, Kaiser A. Very low-voltage digital-audio Δ Σ modulator with 88-dB dynamic range using local switch bootstrapping[J]. IEEE J Solid-State Circuits, 2001, 36(3): 349.

[17]

Gu Weiru, Ye Fan, Ren Junyan. An 11-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation[J]. Journal of Semiconductors, 2014, 35(8): 085006.

[18]

Ogawa T, Kobayashi H, Hotta M. SAR ADC algorithm with redundancy[J]. IEEE APCCAS, 2008: 268.

[19]

Miyahara M, Asada Y, Paik D. A low-noise self-calibrating dynamic comparator for high-speed ADCs[J]. IEEE ASSCC, 2008: 269.

[20]

Yuan J, Svensson C. High-speed CMOS circuit technique[J]. IEEE J Solid-State Circuits, 1989, 24(1): 62.

[21]

Harikumar P, Wikner J J. A 10-bit 50MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer[J]. Integration, the VLSI Journal, 2015, 50: 28.

[22]

ChoS H, Lee C K, Kwon J K. A 550-μ W 10-b 40-MS/s SAR ADC with multistep addition-only digital error correction[J]. IEEE J Solid-State Circuits, 2011, 46(8): 1881.

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M Y Yu, T Li, J Q Yang, S S Zhang, F J Lin, L He. A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process[J]. J. Semicond., 2016, 37(7): 075005. doi: 10.1088/1674-4926/37/7/075005.

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Manuscript received: 23 November 2015 Manuscript revised: Online: Published: 01 July 2016

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