J. Semicond. > Volume 38 > Issue 10 > Article Number: 105002

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

Chenyi Zhou 1, , Zhenghao Lu 2, , , Jiangmin Gu 1, and Xiaopeng Yu 1,

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Abstract: We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices.

Key words: CMOS technologypower amplifierlow voltagehigh efficiencyclass-EEM co-simulation

Abstract: We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices.

Key words: CMOS technologypower amplifierlow voltagehigh efficiencyclass-EEM co-simulation



References:

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[1]

Lin Z C, Mak P I, Martins R P. A sub-GHz multi-ISM-band ZigBee receiver using function-reuse and gain-boosted n-path techniques for IoT applications[J]. IEEE J Solid-State Circuits, 2014, 49: 2990. doi: 10.1109/JSSC.2014.2358560

[2]

Melly T, Porret A S, Enz C C. An ultralow-power UHF transceiver integrated in a standard digital CMOS process: transmitter[J]. IEEE J Solid-state Circuits, 2001, 36: 467. doi: 10.1109/4.910485

[3]

Quinlan P, Crowley P, Chanca M. A Multimode 0.3–200-kb/s transceiver for the 433/868/915-MHz bands in 0.25-μm CMOS[J]. IEEE J Solid-state Circuits, 2004, 39: 2297. doi: 10.1109/JSSC.2004.836330

[4]

El-Desouki M M, Deen M J, Haddara Y M. A fully integrated CMOS power amplifier using superharmonic injection-locking for short-range applications[J]. IEEE Sensors J, 2011, 11: 2149. doi: 10.1109/JSEN.2011.2109708

[5]

Sokal N O. Class-E RF power amplifiers[J]. QEX, 2001: 9.

[6]

Roberts N E, Kines MC, Wentzloff D D. A 380 μW Rx, 2.6 mW Tx 433 MHz FSK transceiver with a 102 dB link budget and bit-level duty cycling. IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Phoenix, Arizona, 2015

[7]

Ghosh A, Dhar A S, Halder A. An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS. 18th International Symposium on VLSI Design and Test, Coimbatore, India, 2014

[8]

Zhu J Y, Wu L J, Zhang X M, et al. A low-power 433 MHz transmitter for battery-less tire pressure monitoring system. 9th IEEE International Conference on ASIC, Xiamen, China, 2011

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C Y Zhou, Z H Lu, J M Gu, X P Yu. A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range[J]. J. Semicond., 2017, 38(10): 105002. doi: 10.1088/1674-4926/38/10/105002.

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History

Manuscript received: 30 March 2017 Manuscript revised: 15 May 2017 Online: Accepted Manuscript: 13 November 2017 Published: 01 October 2017

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