J. Semicond. > Volume 41 > Issue 12 > Article Number: 122403

Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process

Jianwei Wu , Zongguang Yu , , Genshen Hong and Rubin Xie

+ Author Affiliations + Find other works by these authors

PDF

Turn off MathJax

Abstract: In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.

Key words: total ionizing doseRHBPGGNMOSESD ion implantationSTITLPleakage currentDCGS

Abstract: In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.

Key words: total ionizing doseRHBPGGNMOSESD ion implantationSTITLPleakage currentDCGS



References:

[1]

Kepens B. On-chip ESD solutions seminar. SOFICS, Shanghai, 2015

[2]

Xie R B, Ji X M, Wu J W. Research on ESD performance of devices in radiation hardening process. Microprocessors, 2019, 40, 1

[3]

Wang A Z H. On-chip ESD protection for integrated circuits: An IC design perspective. Springer Science & Business Media, 2006

[4]

Zhang L Z, Wang Y, Wang Y Z, et al. Insight into multiple-triggering effect in DTSCRs for ESD protection. J Semicond, 2017, 38, 075001

[5]

Bi X W, Liang H L, Gu X F, et al. Design of novel DDSCR with embedded PNP structure for ESD protection. J Semicond, 2015, 36, 124007

[6]

Mohan N, Kumar A. ESD protection design methodology in deep sub-micron CMOS technologies. Project Report, Course E&CE 730 (Topic 9), 2003, 5

[7]

Jiang Y X, Li J, Ran F, et al. Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology. J Semicond, 2009, 30, 084007

[8]

Chen T Y, Ker M D. Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process. IEEE Trans Semicond Manuf, 2003, 16, 486

[9]

Do K I, Park J G, Kwon M J, et al. Analysis of GGNMOS-based ESD protection device using DCGS variation with robustness. Academic Conference of Korean Institute of Electronic Engineering, 2016, 6, 74

[10]

Krabbenborg B, Beltman R, Wolbert P, et al. Physics of electro-thermal effects in ESD protection devices. J Electrost, 1992, 28, 285

[11]

Chen J Z, Zhang X Y, Amerasekera A, et al. Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits. Proceedings of International Reliability Physics Symposium, 1996

[12]

Ker M D, Chen T Y. Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process. IEEE Trans Electron Devices, 2003, 50, 1050

[13]

Wu D X, Jiang L L, Fan H, et al. Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS. J Semicond, 2013, 34, 024004

[14]

Wu J W, Yu Z G, Hong G S, et al. A method for strengthening the total ionizing dose of 0.18 μm bulk CMOS process. 2018 International Conference on Radiation Effects of Electronic Devices, 2018

[15]

Paul M, Russ C, Kumar B S, et al. Physics of current filamentation in ggNMOS devices under ESD condition revisited. IEEE Trans Electron Devices, 2018, 65, 2981

[16]

Wang Y, Lu G Y, Wang Y Z, et al. Power-rail ESD clamp circuit with parasitic-BJT and channel parallel shunt paths to achieve enhanced robustness. IEICE Trans Electron, 2017, E100.C, 344

[17]

Li L, Zhu K H. ESD performance analysis of gate grounded NMOS devices. Electron Pack, 2011, 11, 18

[18]

Li Z G, Yue S G, Sun Y Z. Research on ESD device design of deep submicron IC. The 16th National Conference on Silicon Materials for Semiconductor Integrated circuits, 2009

[19]

Li Z G, Yue S G, Sun Y S. GDNMOS design for ESD protection in submicron CMOS VLSI. 2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics, 2009, 432

[20]

Shi J. Deep sub-micron ESD GGNMOS layout design and optimization. MATEC Web Conf, 2018, 198, 04009

[21]

Boschke R, Chen S H, Scholz M, et al. ESD ballasting of Ge FinFET ggNMOS devices. 2017 IEEE International Reliability Physics Symposium (IRPS) – Monterey, 2017

[1]

Kepens B. On-chip ESD solutions seminar. SOFICS, Shanghai, 2015

[2]

Xie R B, Ji X M, Wu J W. Research on ESD performance of devices in radiation hardening process. Microprocessors, 2019, 40, 1

[3]

Wang A Z H. On-chip ESD protection for integrated circuits: An IC design perspective. Springer Science & Business Media, 2006

[4]

Zhang L Z, Wang Y, Wang Y Z, et al. Insight into multiple-triggering effect in DTSCRs for ESD protection. J Semicond, 2017, 38, 075001

[5]

Bi X W, Liang H L, Gu X F, et al. Design of novel DDSCR with embedded PNP structure for ESD protection. J Semicond, 2015, 36, 124007

[6]

Mohan N, Kumar A. ESD protection design methodology in deep sub-micron CMOS technologies. Project Report, Course E&CE 730 (Topic 9), 2003, 5

[7]

Jiang Y X, Li J, Ran F, et al. Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology. J Semicond, 2009, 30, 084007

[8]

Chen T Y, Ker M D. Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process. IEEE Trans Semicond Manuf, 2003, 16, 486

[9]

Do K I, Park J G, Kwon M J, et al. Analysis of GGNMOS-based ESD protection device using DCGS variation with robustness. Academic Conference of Korean Institute of Electronic Engineering, 2016, 6, 74

[10]

Krabbenborg B, Beltman R, Wolbert P, et al. Physics of electro-thermal effects in ESD protection devices. J Electrost, 1992, 28, 285

[11]

Chen J Z, Zhang X Y, Amerasekera A, et al. Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits. Proceedings of International Reliability Physics Symposium, 1996

[12]

Ker M D, Chen T Y. Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process. IEEE Trans Electron Devices, 2003, 50, 1050

[13]

Wu D X, Jiang L L, Fan H, et al. Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS. J Semicond, 2013, 34, 024004

[14]

Wu J W, Yu Z G, Hong G S, et al. A method for strengthening the total ionizing dose of 0.18 μm bulk CMOS process. 2018 International Conference on Radiation Effects of Electronic Devices, 2018

[15]

Paul M, Russ C, Kumar B S, et al. Physics of current filamentation in ggNMOS devices under ESD condition revisited. IEEE Trans Electron Devices, 2018, 65, 2981

[16]

Wang Y, Lu G Y, Wang Y Z, et al. Power-rail ESD clamp circuit with parasitic-BJT and channel parallel shunt paths to achieve enhanced robustness. IEICE Trans Electron, 2017, E100.C, 344

[17]

Li L, Zhu K H. ESD performance analysis of gate grounded NMOS devices. Electron Pack, 2011, 11, 18

[18]

Li Z G, Yue S G, Sun Y Z. Research on ESD device design of deep submicron IC. The 16th National Conference on Silicon Materials for Semiconductor Integrated circuits, 2009

[19]

Li Z G, Yue S G, Sun Y S. GDNMOS design for ESD protection in submicron CMOS VLSI. 2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics, 2009, 432

[20]

Shi J. Deep sub-micron ESD GGNMOS layout design and optimization. MATEC Web Conf, 2018, 198, 04009

[21]

Boschke R, Chen S H, Scholz M, et al. ESD ballasting of Ge FinFET ggNMOS devices. 2017 IEEE International Reliability Physics Symposium (IRPS) – Monterey, 2017

[1]

Daoxun Wu, Lingli Jiang, Hang Fan, Jian Fang, Bo Zhang. Analysis on the positive dependence of channel length on ESD failure current of a GGNMOS in a 5 V CMOS. J. Semicond., 2013, 34(2): 024004. doi: 10.1088/1674-4926/34/2/024004

[2]

Zhaonian Yang, Hongxia Liu, Shulong Wang. A low leakage power-rail ESD detection circuit with a modified RC network for a 90-nm CMOS process. J. Semicond., 2013, 34(4): 045010. doi: 10.1088/1674-4926/34/4/045010

[3]

Li Dongmei, Huangfu Liying, Gou Qiujing, Wang Zhihua. Total Ionizing Dose Radiation Effects on MOS Transistors with Different Layouts. J. Semicond., 2007, 28(2): 171.

[4]

Liu Zhangli, Hu Zhiyuan, Zhang Zhengxuan, Shao Hua, Chen Ming, Bi Dawei, Ning Bingxu, Zou Shichang. Gate length dependence of the shallow trench isolation leakage current in an irradiated deep submicron NMOSFET. J. Semicond., 2011, 32(6): 064004. doi: 10.1088/1674-4926/32/6/064004

[5]

Fengying Qiao, Liyang Pan, Dong Wu, Lifang Liu, Jun Xu. A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory. J. Semicond., 2014, 35(2): 024003. doi: 10.1088/1674-4926/35/2/024003

[6]

Bu Jianhui, Bi Jinshun, Liu Mengxin, Han Zhengsheng. A total dose radiation model for deep submicron PDSOI NMOS. J. Semicond., 2011, 32(1): 014002. doi: 10.1088/1674-4926/32/1/014002

[7]

Xiuwen Bi, Hailian Liang, Xiaofeng Gu, Long Huang. Design of novel DDSCR with embedded PNP structure for ESD protection. J. Semicond., 2015, 36(12): 124007. doi: 10.1088/1674-4926/36/12/124007

[8]

Xue Jiying, Li Tao, Yu Zhiping. Accurate and fast table look-up models for leakage current analysis in 65 nm CMOS technology. J. Semicond., 2009, 30(2): 024004. doi: 10.1088/1674-4926/30/2/024004

[9]

O.Ya Olikh, K.V. Voitenko, R.M. Burbelo, JaM. Olikh. Effect of ultrasound on reverse leakage current of silicon Schottky barrier structure. J. Semicond., 2016, 37(12): 122002. doi: 10.1088/1674-4926/37/12/122002

[10]

Wanjun Chen, Jing Zhang, Bo Zhang, Kevin Jing Chen . Fluorine-plasma surface treatment for gate forward leakage current reduction in AlGaN/GaN HEMTs. J. Semicond., 2013, 34(2): 024003. doi: 10.1088/1674-4926/34/2/024003

[11]

Huaguo Liang, Hui Xu, Zhengfeng Huang, Maoxiang Yi. A low-leakage and NBTI-mitigated N-type domino logic. J. Semicond., 2014, 35(1): 015009. doi: 10.1088/1674-4926/35/1/015009

[12]

Gong Na, Wang Jinhui, Guo Baozeng, Pang Jiao. Temperature and Process Variations Aware Dual Threshold Voltage Footed Domino Circuits Leakage Management. J. Semicond., 2008, 29(12): 2364.

[13]

Guo Baozeng, Gong Na, Wang Jinhui. Designing Leakage-Tolerant and Noise-Immune Enhanced Low Power Wide OR Dominos in Sub-70nm CMOS Technologies. J. Semicond., 2006, 27(5): 804.

[14]

Junjun Yuan, Zebo Fang, Yanyan Zhu, Bo Yao, Shiyan Liu, Gang He, Yongsheng Tan. Current mechanism and band alignment of Al(Pt)/HfGdO/Ge capacitors. J. Semicond., 2016, 37(3): 034006. doi: 10.1088/1674-4926/37/3/034006

[15]

Huang Huixiang, Liu Zhangli, Hu Zhiyuan, Zhang Zhengxuan, Chen Ming, Bi Dawei, Zou Shichang. Influence of drain and substrate bias on the TID effect for deep submicron technology devices. J. Semicond., 2012, 33(4): 044008. doi: 10.1088/1674-4926/33/4/044008

[16]

Chen Liu, Yuming Zhang, Yimen Zhang, Hongliang Lü, Bin Lu. Temperature dependent interfacial and electrical characteristics during atomic layer deposition and annealing of HfO2 films in p-GaAs metal-oxide-semiconductor capacitors. J. Semicond., 2015, 36(12): 124003. doi: 10.1088/1674-4926/36/12/124003

[17]

Neha Gupta, Priyanka Parihar, Vaibhav Neema. Application of source biasing technique for energy efficient DECODER circuit design: memory array application. J. Semicond., 2018, 39(4): 045001. doi: 10.1088/1674-4926/39/4/045001

[18]

Jin Guofen, Wu Huizhen, Liang Jun, Lao yanfeng, Yu Ping, Xu Tianning. Electrical Characteristics of Cubic ZnMgO. J. Semicond., 2007, 28(S1): 167.

[19]

Jun Ma, Yawei Guo, Yue Wu, Xu Cheng, Xiaoyang Zeng. A 1-V 10-bit 80-MS/s 1.6-mW SAR ADC in 65-nm GP CMOS. J. Semicond., 2013, 34(8): 085014. doi: 10.1088/1674-4926/34/8/085014

[20]

Gao Yong, Liu Jing, Ma Li, Yu Mingbin. Numerical Simulation and Analysis of SiGeC/Si Heterojunction Power Diodes. J. Semicond., 2006, 27(6): 1068.

Search

Advanced Search >>

GET CITATION

J W Wu, Z G Yu, G S Hong, R B Xie, Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process[J]. J. Semicond., 2020, 41(12): 122403. doi: 10.1088/1674-4926/41/12/122403.

Export: BibTex EndNote

Article Metrics

Article views: 1039 Times PDF downloads: 26 Times Cited by: 0 Times

History

Manuscript received: 30 March 2020 Manuscript revised: 27 April 2020 Online: Accepted Manuscript: 18 June 2020 Uncorrected proof: 05 November 2020 Published: 08 December 2020

Email This Article

User name:
Email:*请输入正确邮箱
Code:*验证码错误