J. Semicond. > Volume 39 > Issue 2 > Article Number: 021001

Concept and design of super junction devices

Bo Zhang , , Wentong Zhang , Ming Qiao , Zhenya Zhan and Zhaoji Li

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Abstract: The super junction (SJ) has been recognized as the " milestone” of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer (VSL). The basic structure of the SJ is a typical junction-type VSL (J-VSL) with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL (R-VSL) with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the J-VSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional " silicon limit” relationship of RonVB2.5, showing a quasi-linear relationship of RonVB1.03.

Key words: super junctionsilicon limitpower semiconductor devicedesign theory

Abstract: The super junction (SJ) has been recognized as the " milestone” of the power MOSFET, which is the most important innovation concept of the voltage-sustaining layer (VSL). The basic structure of the SJ is a typical junction-type VSL (J-VSL) with the periodic N and P regions. However, the conventional VSL is a typical resistance-type VSL (R-VSL) with only an N or P region. It is a qualitative change of the VSL from the R-VSL to the J-VSL, introducing the bulk depletion to increase the doping concentration and optimize the bulk electric field of the SJ. This paper firstly summarizes the development of the SJ, and then the optimization theory of the SJ is discussed for both the vertical and the lateral devices, including the non-full depletion mode, the minimum specific on-resistance optimization method and the equivalent substrate model. The SJ concept breaks the conventional " silicon limit” relationship of RonVB2.5, showing a quasi-linear relationship of RonVB1.03.

Key words: super junctionsilicon limitpower semiconductor devicedesign theory



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[1]

Zhang B, Zhang W T, Qiao M. Theory and optimization of the power super junction device[J]. Sci Sin-Phys Mech Astron, 2016, 46: 107302.

[2]

Zhang B, Luo X R, Li Z J. Electric field optimization technology for power semiconductor devices. Chengdu: UESTC Press, 2016 (in Chinese)

[3]

Chen X B. Superjunction device[J]. Power Electron, 2008, 42(12): 2.

[4]

Chen X B. Semiconductor power devices with alternating conductivity type high-voltage breakdown region. US Patient, US5216275, 1993

[5]

Chen X B, Mawby P A, Board K. Theory of a novel voltage-sustaining layer for power devices[J]. Microelectron J, 1998, 29(12): 1005. doi: 10.1016/S0026-2692(98)00065-2

[6]

Coe D J. High voltage semiconductor device. USA Patent, US4754310, 1988

[7]

Tihanyi J. Power MOSFET. USA Patent, US5438215, 1995

[8]

Fujihira T. Theory of semiconductor superjunction devices[J]. Jpn J Appl Phys, 1997, 36(10): 6254.

[9]

Deboy G, Marz M, Stengl J P. A new generation of high voltage MOSFETs breaks the limit line of silicon[J]. IEEE International Electron Devices Meeting (IEDM), 1998: 683.

[10]

Lorenz L, Deboy G, Knapp A. CooLMOSTM: a new milestone in high voltage power MOS[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 1999: 3.

[11]

Zhang W T, Zhang B. Theory of superjunction with NFD and FD modes based on normalized breakdown voltage[J]. IEEE Trans Electron Devices, 2015, 62(12): 4114. doi: 10.1109/TED.2015.2491360

[12]

Kawashima Y, Inomata H, Murakawa K. Narrow-pitch n-channel superjunction UMOSFET for 40–60 V automotive application[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010: 329.

[13]

Yamauchi S, Shibata T, Nogami S. 200 V super junction MOSFET fabricated by high aspect ratio trench filling[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2006: 1.

[14]

Saito W, Omura I, Aida S. A 15.5 mΩ·cm2 680 V superjunction MOSFET reduced on-resistance by lateral pitch narrowing[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2006: 1.

[15]

Sakakibara J, Noda Y, Shibata T. 600 V-class super junction MOSFET with high aspect ratio P/N columns structure[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2008: 299.

[16]

Rutter P, Peake S T. Low voltage trenchMOS combining low specific RDS (on) and QG FOM[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2010: 325.

[17]

Okubo H, Kobayashi K, Kawashima Y. Ultralow on-resistance 30–40 V UMOSFET by 2-D scaling of ion-implanted superjunction structure[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2013: 87.

[18]

Miura Y, Ninomiya H, Kobayashi K. High performance superjunction UMOSFETs with split P-columns fabricated by multi-ion-implantations[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2005: 39.

[19]

Ninomiya H, Miura Y, Kobayashi K. Ultra-low on-resistance 60–100 V superjunction UMOSFETs fabricated by multiple ion-implantation[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 177.

[20]

Dalen R, Rochefort C. Electrical characterisation of vertical vapor phase doped (VPD) RESURF MOSFETs[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 451.

[21]

Dalen R, Rochefort C. Vertical multi-RESURF MOSFETs exhibiting record low specific resistance[J]. IEEE International Electron Devices Meeting (IEDM), 2003: 31.1.1.

[22]

Rochefort C, Dalen R. Vertical RESURF diodes manufactured by deep-trench etch and vapor-phase doping[J]. IEEE Electron Device Lett, 2004, 25(2): 73. doi: 10.1109/LED.2003.822649

[23]

Hu C M. Optimum doping profile for minimum ohmic resistance and high-breakdown voltage[J]. IEEE Trans Electron Devices, 1979, 26(3): 243. doi: 10.1109/T-ED.1979.19416

[24]

Gan K P, Yang X, Liang Y C. A simple technology for superjunction device fabrication: polyflanked VDMOSFET[J]. IEEE Electron Device Letters, 2002, 23(10): 627. doi: 10.1109/LED.2002.803770

[25]

Hattori Y, Nakashima K, Kuwahara M. Design of a 200 V super junction MOSFET with n-buffer regions and its fabrication by trench filling[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 189.

[26]

Kurosaki T, Shishido H, Kitada M. 200 V multi RESURF trench MOSFET (MR-TMOS)[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2003: 211.

[27]

Nitta T, Minato T, Yano M. Experimental results and simulation analysis of 250 V super trench power MOSFET (STM)[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2000: 77.

[28]

Rochefort C, Dalen R. A scalable trench etch based process for high voltage vertical RESURF MOSFETs[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2005: 35.

[29]

Iwamoto S, Takahashi K, Kuribayashi H. Above 500 V class superjunction MOSFETs fabricated by deep trench etching and epitaxial growth[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2005: 31.

[30]

Rüb M, Bär M, Deboy G. 550 V superjunction 3.9 Ω·mm2 transistor formed by 25 MeV masked boron implantation[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 455.

[31]

Lee SC, Oh K H, Kim S S. 650 V superjunction MOSFET using universal charge balance concept through drift region[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2014: 83.

[32]

Onishi Y, Iwamoto S, Sato T. 24 mΩ·cm2 680 V silicon superjunction MOSFET[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2002: 241.

[33]

Saito W, Omura L, Aida S. A 20 mΩ·cm2 600 V-class superjunction MOSFET[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2004: 459.

[34]

Takahashi K, Kuribayashi H, Kawashima T. 20 mΩ·cm2 660 V super junction MOSFETs fabricated by deep trench etching and epitaxial growth[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2006: 1.

[35]

Moens P, Bogman F, Ziad H. UltiMOS: a local charge-balanced trench-based 600 V super-junction device[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2011: 304.

[36]

Sugi A, Takei M, Takahashi K. Super junction MOSFETs above 600 V with parallel gate structure fabricated by deep trench etching and epitaxial growth[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2008: 165.

[37]

Tamaki T, Nakazawa Y, Kanai H. Vertical charge imbalance effect on 600 V-class trench-filling superjunction power MOSFETs[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2011: 308.

[38]

Kagata Y, Oda Y, Hayashi K. 600 V-class trench-filling super junction power MOSFETs for low loss and low leakage current[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 2013: 225.

[39]

Jung E S, Kyoung S S, Kang E G. Design and fabrication of super junction MOSFET based on trench filling and bottom implantation process[J]. J Electr Eng Technol, 2014, 9(3): 964. doi: 10.5370/JEET.2014.9.3.964

[40]

Shenoy P M, Bhalla A, Dolny G. Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET[J]. IEEE International Symposium on Power Semiconductor Devices & IC's (ISPSD), 1999: 99.

[41]

Chen X B, Sin J K O. Optimization of the specific on-resistance of the COOLMOSTM[J]. IEEE Trans Electron Devices, 2001, 48(2): 344. doi: 10.1109/16.902737

[42]

Buzzo M, Rub M, Ciappa M. Characterization of 2D dopant profiles for the design of proton implanted high-voltage super junction[J]. International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2005: 285.

[43]

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B Zhang, W T Zhang, M Qiao, Z Y Zhan, Z J Li. Concept and design of super junction devices[J]. J. Semicond., 2018, 39(2): 021001. doi: 10.1088/1674-4926/39/2/021001.

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Manuscript received: 21 September 2017 Manuscript revised: 01 November 2017 Online: Uncorrected proof: 24 January 2018 Accepted Manuscript: 01 February 2018 Published: 02 February 2018

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