J. Semicond. > Volume 37 > Issue 10 > Article Number: 106002

Novel through-silicon vias for enhanced signal integrity in 3D integrated systems

Runiu Fang 1, , Xin Sun 2, , Min Miao 3, , and Yufeng Jin 1, 4, ,

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Abstract: In this paper, a new type of through-silicon via (TSV) for via-first process namely bare TSV, is proposed and analyzed with the aim of mitigating noise coupling problems in 3D integrated systems for advanced technology nodes. The bare TSVs have no insulation layers, and are divided into two types: bare signal TSVs and bare ground TSVs. First, by solving Poisson's equation for cylindrical P-N junctions, the bare signal TSVs are shown to be equivalent to conventional signal TSVs according to the simulation results. Then the bare ground TSV is proved to have improved noise-absorption capability when compared with a conventional ground TSV. Also, the proposed bare TSVs offer more advantages to circuits than other noise isolation methods, because the original circuit design, routing and placement can be retained after the application of the bare TSVs.

Key words: through-silicon-viascrosstalkMOS capacitancePoisson's equation

Abstract: In this paper, a new type of through-silicon via (TSV) for via-first process namely bare TSV, is proposed and analyzed with the aim of mitigating noise coupling problems in 3D integrated systems for advanced technology nodes. The bare TSVs have no insulation layers, and are divided into two types: bare signal TSVs and bare ground TSVs. First, by solving Poisson's equation for cylindrical P-N junctions, the bare signal TSVs are shown to be equivalent to conventional signal TSVs according to the simulation results. Then the bare ground TSV is proved to have improved noise-absorption capability when compared with a conventional ground TSV. Also, the proposed bare TSVs offer more advantages to circuits than other noise isolation methods, because the original circuit design, routing and placement can be retained after the application of the bare TSVs.

Key words: through-silicon-viascrosstalkMOS capacitancePoisson's equation



References:

[1]

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[2]

Kim J S, Oh C S, Lee H. A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4 128 I/Os using TSV based stacking[J]. IEEE J Solid-State Circuits, 2012, 47(1): 107. doi: 10.1109/JSSC.2011.2164731

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Jeddeloh J, Keeth B. Hybrid memory cube new DRAM architecture increases density and performance. Symposium on VLSI Technology (VLSIT), 2012: 87

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Farooq M G, Graves-Abe T L, Landers W F, et al. 3D copper TSV integration, testing and reliability. IEEE International Electron Devices Meeting (IEDM), 2011: 7.1.1

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Black B. Die stacking and high-bandwidth memory. International Conference on 3D Architectures for Semiconductor Integration and Packaging (3D ASIP), 2013

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Shi X Q, Sun P, Tsui Y K, et al. Development of CMOS-process-compatible interconnect technology for 3D-stacking of NAND flash memory chips. Electronic Components and Technology Conference (ECTC), 201: 74

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Lee D U, Kim K W, Kim K W, et al. 25.2 A 1.2 V 8 Gb 8-channel 128 GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29 nm process and TSV. Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014: 432

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International Technology Roadmap for Semiconductors. 2013 Edition, Interconnect Chapter (ITRS), 2013: 12

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Cho J, Song E, Yoon K. Modeling and analysis of through-silicon via (TSV) noise coupling and suppression using a guard ring[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2011, 1(2): 220. doi: 10.1109/TCPMT.2010.2101892

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Fang R, Sun X, Jin Y, et al. Modeling and analysis of TSV noise coupling and suppression methods for 20 nm node and beyond. International Conference on Electronic Packaging Technology (ICEPT), 2014: 783

[12]

Lin L J H, Chiou Y P. 3-D transient analysis of TSV-induced substrate noise: improved noise reduction in 3-D-ICs with incorporation of guarding structures[J]. IEEE Electron Device Lett, 2014, 35(6): 660. doi: 10.1109/LED.2014.2318301

[13]

Gu X, Silberman J, Liu Y, et al. Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts. Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012: 75

[14]

Khan N H, Alam S M, Hassoun S. GND plugs: a superior technology to mitigate TSV-induced substrate noise[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2013, 3(5): 849. doi: 10.1109/TCPMT.2013.2241178

[15]

Khan N H, Alam S M, Hassoun S. Through-silicon via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. 3D System Integration (3DIC), 2009: 1

[16]

Zhao Yingbo, Dong Gang, Yang Yintang. Analysis and optimization of TSV-TSV coupling in three-dimensional integrated circuits[J]. Journal of Semiconductors, 2015, 36(4): 045011. doi: 10.1088/1674-4926/36/4/045011

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Laviron C, Dunne B, Lapras V R, et al. Via first approach optimization for through silicon via applications. Electronic Components and Technology Conference (ECTC), 2009: 14

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Henry D, Baillin X, Lapras V, et al. Via first technology development based on high aspect ratio trenches filled with doped polysilicon. Electronic Components and Technology Conference (ECTC), 2007: 830

[19]

Chow E M, Chandrasekaran V, Partridge A. Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates[J]. Journal of Microelectromechanical Systems, 2002, 11(6): 631. doi: 10.1109/JMEMS.2002.805206

[20]

Ji F, Leppävuori S, Luusua I. Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging[J]. Sensors and Actuators A, 2008, 142(1): 405. doi: 10.1016/j.sna.2007.02.030

[21]

Fripp A L. Dependence of resistivity on the doping level of polycrystalline silicon[J]. J Appl Phys, 1975, 46(3): 1240. doi: 10.1063/1.321687

[22]

Chen Y, Kursun E, Motschman D. Through silicon via aware design planning for thermally efficient 3-D integrated circuits[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(9): 1335. doi: 10.1109/TCAD.2013.2261120

[23]

Engin A E, Raghavan N S. Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design. 3D System Integration Conference (3DIC), 2012: 1

[24]

Yang D C, Xie J, Swaminathan M. A rigorous model for through-silicon vias with ohmic contact in silicon interposer[J]. IEEE Microwave and Wireless Components Letters, 2013, 23(8): 385. doi: 10.1109/LMWC.2013.2270459

[25]

Bandyopadhyay T, Han K J, Chung D. Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2011, 1(6): 893. doi: 10.1109/TCPMT.2011.2120607

[26]

Fang R, Sun X, Miao M. Characteristics of coupling capacitance between signal-ground TSVs considering MOS effect in silicon interposers[J]. IEEE Trans Electron Devices, 2015, 62(12): 4161. doi: 10.1109/TED.2015.2494538

[27]

Liu Song, Shan Guangbao, Xie Chengmin. A transmission line-type electrical model for tapered TSV considering MOS effect and frequency-dependent behavior[J]. Journal of Semiconductors, 2015, 36(2): 024009. doi: 10.1088/1674-4926/36/2/024009

[28]

Fang R, Miao M, Sun X, et al. Investigation of a TSV-RDL in-line fault-diagnosis system and test methodology for wafer-level commercial production. Electronic Components and Technology Conference (ECTC), 2014: 641

[29]

Katti G, Mercha A, Stucchi M, et al. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections. International Interconnect Technology Conference (IITC), 2010: 1

[30]

Sun X, Fang R, Zhu Y. Measurement-based electrical characterization of through silicon vias and transmission lines for 3D integration[J]. Microelectronic Engineering, 2016, 149(X): 145.

[31]

Nakamura T, Kitada H, Mizushima Y. Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects[J]. IEEE International Systems Integration Conference (3DIC), 2012, 149: 145.

[32]

Zhang L, Li H Y, Gao S. Achieving stable through-silicon via (TSV) capacitance with oxide fixed charge[J]. IEEE Electron Device Lett, 2011, 32(5): 668. doi: 10.1109/LED.2011.2111351

[33]

Sun X, Ji M, Ma S, et al. Electrical characterization of sidewall insulation layer of TSV. International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), 2010: 77

[34]

Achuthan M K, Bhat M K A K N. Fundamentals of semiconductor devices. McGraw-Hill College, 2006: 75

[35]

ANSYS HFSS 14.0 User Guide

[36]

Kim J, Pak J S, Cho J. High-frequency scalable electrical model and analysis of a through silicon via (TSV)[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2011, 1(2): 181. doi: 10.1109/TCPMT.2010.2101890

[1]

Kang U, Chung H, Heo S. 8 Gb 3-D DDR3 DRAM using through-silicon-via technology[J]. IEEE J Solid-State Circuits, 2010, 45: 111. doi: 10.1109/JSSC.2009.2034408

[2]

Kim J S, Oh C S, Lee H. A 1.2 V 12.8 GB/s 2 Gb mobile wide-I/O DRAM with 4 128 I/Os using TSV based stacking[J]. IEEE J Solid-State Circuits, 2012, 47(1): 107. doi: 10.1109/JSSC.2011.2164731

[3]

Jeddeloh J, Keeth B. Hybrid memory cube new DRAM architecture increases density and performance. Symposium on VLSI Technology (VLSIT), 2012: 87

[4]

Farooq M G, Graves-Abe T L, Landers W F, et al. 3D copper TSV integration, testing and reliability. IEEE International Electron Devices Meeting (IEDM), 2011: 7.1.1

[5]

Black B. Die stacking and high-bandwidth memory. International Conference on 3D Architectures for Semiconductor Integration and Packaging (3D ASIP), 2013

[6]

Shi X Q, Sun P, Tsui Y K, et al. Development of CMOS-process-compatible interconnect technology for 3D-stacking of NAND flash memory chips. Electronic Components and Technology Conference (ECTC), 201: 74

[7]

Saban K. Xilinx stacked silicon interconnect technology delivers breakthrough FPGA capacity, bandwidth, and power efficiency. Xilinx White paper: Vertex-7 FPGAs, 2010: 1

[8]

Lee D U, Kim K W, Kim K W, et al. 25.2 A 1.2 V 8 Gb 8-channel 128 GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29 nm process and TSV. Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014: 432

[9]

International Technology Roadmap for Semiconductors. 2013 Edition, Interconnect Chapter (ITRS), 2013: 12

[10]

Cho J, Song E, Yoon K. Modeling and analysis of through-silicon via (TSV) noise coupling and suppression using a guard ring[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2011, 1(2): 220. doi: 10.1109/TCPMT.2010.2101892

[11]

Fang R, Sun X, Jin Y, et al. Modeling and analysis of TSV noise coupling and suppression methods for 20 nm node and beyond. International Conference on Electronic Packaging Technology (ICEPT), 2014: 783

[12]

Lin L J H, Chiou Y P. 3-D transient analysis of TSV-induced substrate noise: improved noise reduction in 3-D-ICs with incorporation of guarding structures[J]. IEEE Electron Device Lett, 2014, 35(6): 660. doi: 10.1109/LED.2014.2318301

[13]

Gu X, Silberman J, Liu Y, et al. Mitigating TSV-induced substrate noise coupling in 3-D IC using buried interface contacts. Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012: 75

[14]

Khan N H, Alam S M, Hassoun S. GND plugs: a superior technology to mitigate TSV-induced substrate noise[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2013, 3(5): 849. doi: 10.1109/TCPMT.2013.2241178

[15]

Khan N H, Alam S M, Hassoun S. Through-silicon via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. 3D System Integration (3DIC), 2009: 1

[16]

Zhao Yingbo, Dong Gang, Yang Yintang. Analysis and optimization of TSV-TSV coupling in three-dimensional integrated circuits[J]. Journal of Semiconductors, 2015, 36(4): 045011. doi: 10.1088/1674-4926/36/4/045011

[17]

Laviron C, Dunne B, Lapras V R, et al. Via first approach optimization for through silicon via applications. Electronic Components and Technology Conference (ECTC), 2009: 14

[18]

Henry D, Baillin X, Lapras V, et al. Via first technology development based on high aspect ratio trenches filled with doped polysilicon. Electronic Components and Technology Conference (ECTC), 2007: 830

[19]

Chow E M, Chandrasekaran V, Partridge A. Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates[J]. Journal of Microelectromechanical Systems, 2002, 11(6): 631. doi: 10.1109/JMEMS.2002.805206

[20]

Ji F, Leppävuori S, Luusua I. Fabrication of silicon based through-wafer interconnects for advanced chip scale packaging[J]. Sensors and Actuators A, 2008, 142(1): 405. doi: 10.1016/j.sna.2007.02.030

[21]

Fripp A L. Dependence of resistivity on the doping level of polycrystalline silicon[J]. J Appl Phys, 1975, 46(3): 1240. doi: 10.1063/1.321687

[22]

Chen Y, Kursun E, Motschman D. Through silicon via aware design planning for thermally efficient 3-D integrated circuits[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2013, 32(9): 1335. doi: 10.1109/TCAD.2013.2261120

[23]

Engin A E, Raghavan N S. Metal semiconductor (MES) TSVs in 3D ICs: Electrical modeling and design. 3D System Integration Conference (3DIC), 2012: 1

[24]

Yang D C, Xie J, Swaminathan M. A rigorous model for through-silicon vias with ohmic contact in silicon interposer[J]. IEEE Microwave and Wireless Components Letters, 2013, 23(8): 385. doi: 10.1109/LMWC.2013.2270459

[25]

Bandyopadhyay T, Han K J, Chung D. Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2011, 1(6): 893. doi: 10.1109/TCPMT.2011.2120607

[26]

Fang R, Sun X, Miao M. Characteristics of coupling capacitance between signal-ground TSVs considering MOS effect in silicon interposers[J]. IEEE Trans Electron Devices, 2015, 62(12): 4161. doi: 10.1109/TED.2015.2494538

[27]

Liu Song, Shan Guangbao, Xie Chengmin. A transmission line-type electrical model for tapered TSV considering MOS effect and frequency-dependent behavior[J]. Journal of Semiconductors, 2015, 36(2): 024009. doi: 10.1088/1674-4926/36/2/024009

[28]

Fang R, Miao M, Sun X, et al. Investigation of a TSV-RDL in-line fault-diagnosis system and test methodology for wafer-level commercial production. Electronic Components and Technology Conference (ECTC), 2014: 641

[29]

Katti G, Mercha A, Stucchi M, et al. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections. International Interconnect Technology Conference (IITC), 2010: 1

[30]

Sun X, Fang R, Zhu Y. Measurement-based electrical characterization of through silicon vias and transmission lines for 3D integration[J]. Microelectronic Engineering, 2016, 149(X): 145.

[31]

Nakamura T, Kitada H, Mizushima Y. Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects[J]. IEEE International Systems Integration Conference (3DIC), 2012, 149: 145.

[32]

Zhang L, Li H Y, Gao S. Achieving stable through-silicon via (TSV) capacitance with oxide fixed charge[J]. IEEE Electron Device Lett, 2011, 32(5): 668. doi: 10.1109/LED.2011.2111351

[33]

Sun X, Ji M, Ma S, et al. Electrical characterization of sidewall insulation layer of TSV. International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), 2010: 77

[34]

Achuthan M K, Bhat M K A K N. Fundamentals of semiconductor devices. McGraw-Hill College, 2006: 75

[35]

ANSYS HFSS 14.0 User Guide

[36]

Kim J, Pak J S, Cho J. High-frequency scalable electrical model and analysis of a through silicon via (TSV)[J]. IEEE Trans Components, Packaging and Manufacturing Technology, 2011, 1(2): 181. doi: 10.1109/TCPMT.2010.2101890

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R N Fang, X Sun, M Miao, Y F Jin. Novel through-silicon vias for enhanced signal integrity in 3D integrated systems[J]. J. Semicond., 2016, 37(10): 106002. doi: 10.1088/1674-4926/37/10/106002.

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Manuscript received: 17 February 2016 Manuscript revised: 20 April 2016 Online: Published: 01 October 2016

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