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A 256 Gb/s electronic−photonic monolithically integrated transceiver in 45 nm CMOS

Ang Li1, 3, 4, §, Qianli Ma2, 3, §, Yujun Xie1, §, Yongliang Xiong2, 3, Yingjie Ma2, 3, Han Liu2, 3, Ye Jin1, 3, 4, Menghan Yang1, 3, 4, Guike Li2, 3, Haoran Yin2, 3, Minye Zhu2, 3, Yang Qu1, Peng Wang1, Daofa Wang1, 3, 4, Wei Li1, 3, 4, Liyuan Liu2, 3, Nan Qi2, 3, and Ming Li1, 3, 4,

+ Author Affiliations

 Corresponding author: Nan Qi, qinan@semi.ac.cn; Ming Li, ml@semi.ac.cn

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[1]
Plant D V, Morsy-Osman M, Chagnon M. Optical communication systems for datacenter networks. 2017 Optical Fiber Communications Conference and Exhibition (OFC), 2017, 1
[2]
Atabaki A H, Moazeni S, Pavanello F, et al. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip. Nature, 2018, 556(7701), 349 doi: 10.1038/s41586-018-0028-z
[3]
Gonzalez J, Palma M G, Hattink M, et al. Optically connected memory for disaggregated data centers. Journal of Parallel and Distributed Computing, 2022, 163, 300 doi: 10.1016/j.jpdc.2022.01.013
[4]
Minkenberg C, Krishnaswamy R, Zilkie A, et al. Co-packaged datacenter optics: Opportunities and challenges. IET Optoelectronics, 2021, 15(2), 77 doi: 10.1049/ote2.12020
[5]
Meade R, Ardalan S, Davenport M, et al. TeraPHY: a high-density electronic-photonic chiplet for optical I/O from a multi-chip module. 2019 Optical Fiber Communications Conference and Exhibition (OFC), 2019, 1
[6]
Hirokawa T, Bian Y, Giewont K, et al. Latest progress and challenges in 300 mm monolithic silicon photonics manufacturing. Optical Fiber Communication Conference. Optica Publishing Group, 2024, Th3H. 2
[7]
Sun C, Wade M, Georgas M, et al. A 45 nm CMOS-SOI monolithic photonics platform with bit-statistics-based resonant microring thermal tuning. IEEE Journal of Solid-State Circuits, 2016, 51(4), 893 doi: 10.1109/JSSC.2016.2519390
[8]
Ma Q, Li A, Xiong Y, et al. A 200Gb/s, 3.5pJ/bit monolithically integrated WDM Si-Photonic transceiver for chiplet optical I/O. 2024 IEEE Asian Solid-State Circuits Conference(ASSCC) (submitted
[9]
Levy C S, Xuan Z, Sharma J, et al. 8-λ×50 Gbps/λ heterogeneously-integrated Si-Ph DWDM transmitter. IEEE Journal of Solid-State Circuits, 2024, 59, 690
[10]
Xuan Z, Balamurugan G, Huang D N, et al. A 256 Gbps heterogeneously integrated silicon photonic microring-based DWDM receiver suitable for in-package optical I/O. 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, 1 doi: 10.23919/VLSITechnologyandCir57934.2023.10185280
[11]
Raj M, Xie C, Bekele A, et al. A 0.96pJ/b 7× 50Gb/s-per-fiber WDM receiver with stacked 7nm CMOS and 45nm silicon photonic dies. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023, 11 doi: 10.1109/ISSCC42615.2023.10067617
[12]
Sun C. Photonics for die-to-die interconnects: Links and optical I/O chiplets. 2024 IEEE International Solid-State Circuits Conference (ISSCC), F1.7
[13]
Moralis-Pegios M, Pitris S, Alexoudi T, et al. 4-channel 200 Gb/s WDM O-band silicon photonic transceiver sub-assembly. Optics Express, 2020, 28(4), 5706 doi: 10.1364/OE.373454
Fig. 1.  (Color online) Micrograph of the proposed EPIC and its block diagram.

Fig. 2.  (Color online) Measured optical spectra of the 4-channel transmitter (TX) and receiver (RX) from through port.

Fig. 3.  (Color online) Measured eye diagrams of the 4-channel transmitter (TX) and receiver (RX) working at 64 Gb/s NRZ per channel.

Table 1.   Performance summary and comparison to other works.

Intel
JSSC 23-24[9, 10]
AMD
ISSCC 23[11]
Ayar Labs
ISSCC 24[12]
IMEC
OE 20[13]
This work
Laser band O O O O O
Integration approach Flip-chip Flip-chip Monolithic Wire-bonding Monolithic
EIC process 28 nm CMOS 7 nm FinFET
45 nm CMOS SOI 55 nm BiCMOS 45 nm CMOS SOI
Data rate per channel (Gb/s) 50 (TX)
32 (RX)
50 (RX) 32 (TX)
32 (RX)
50 (TX)
50 (RX)
64 (TX)
64 (RX)
Total bandwidth
(Gb/s)
400 (TX)
256 (RX)
350 (RX) 256 (TX)
256 (RX)
200 (TX)
200 (RX)
256 (TX)
256 (RX)
TX ER (dB) 5 N/A 5.6 3.2 7
Bandwidth densitya (Tb/(s∙mm2)) 0.03 (TX + RX)b N/Rc >1 (TX + RX) 0.02 (TX + RX)d 0.226 (TX + RX)
Energy efficiency
(pJ/b)
2.5 (TX)
3.8 (RX)
0.96 (RX) 1.87 (TX)
2.09 (RX)
2.0 (TX)
2.2 (RX)
1.6 (TX)
1.25 (RX)
a Bandwidth density = Total bandwidth/Area (EIC + PIC).
b Calculate from the chip projected area.
c Not report.
d Calculate from the data in the article.
DownLoad: CSV
[1]
Plant D V, Morsy-Osman M, Chagnon M. Optical communication systems for datacenter networks. 2017 Optical Fiber Communications Conference and Exhibition (OFC), 2017, 1
[2]
Atabaki A H, Moazeni S, Pavanello F, et al. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip. Nature, 2018, 556(7701), 349 doi: 10.1038/s41586-018-0028-z
[3]
Gonzalez J, Palma M G, Hattink M, et al. Optically connected memory for disaggregated data centers. Journal of Parallel and Distributed Computing, 2022, 163, 300 doi: 10.1016/j.jpdc.2022.01.013
[4]
Minkenberg C, Krishnaswamy R, Zilkie A, et al. Co-packaged datacenter optics: Opportunities and challenges. IET Optoelectronics, 2021, 15(2), 77 doi: 10.1049/ote2.12020
[5]
Meade R, Ardalan S, Davenport M, et al. TeraPHY: a high-density electronic-photonic chiplet for optical I/O from a multi-chip module. 2019 Optical Fiber Communications Conference and Exhibition (OFC), 2019, 1
[6]
Hirokawa T, Bian Y, Giewont K, et al. Latest progress and challenges in 300 mm monolithic silicon photonics manufacturing. Optical Fiber Communication Conference. Optica Publishing Group, 2024, Th3H. 2
[7]
Sun C, Wade M, Georgas M, et al. A 45 nm CMOS-SOI monolithic photonics platform with bit-statistics-based resonant microring thermal tuning. IEEE Journal of Solid-State Circuits, 2016, 51(4), 893 doi: 10.1109/JSSC.2016.2519390
[8]
Ma Q, Li A, Xiong Y, et al. A 200Gb/s, 3.5pJ/bit monolithically integrated WDM Si-Photonic transceiver for chiplet optical I/O. 2024 IEEE Asian Solid-State Circuits Conference(ASSCC) (submitted
[9]
Levy C S, Xuan Z, Sharma J, et al. 8-λ×50 Gbps/λ heterogeneously-integrated Si-Ph DWDM transmitter. IEEE Journal of Solid-State Circuits, 2024, 59, 690
[10]
Xuan Z, Balamurugan G, Huang D N, et al. A 256 Gbps heterogeneously integrated silicon photonic microring-based DWDM receiver suitable for in-package optical I/O. 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, 1 doi: 10.23919/VLSITechnologyandCir57934.2023.10185280
[11]
Raj M, Xie C, Bekele A, et al. A 0.96pJ/b 7× 50Gb/s-per-fiber WDM receiver with stacked 7nm CMOS and 45nm silicon photonic dies. 2023 IEEE International Solid-State Circuits Conference (ISSCC), 2023, 11 doi: 10.1109/ISSCC42615.2023.10067617
[12]
Sun C. Photonics for die-to-die interconnects: Links and optical I/O chiplets. 2024 IEEE International Solid-State Circuits Conference (ISSCC), F1.7
[13]
Moralis-Pegios M, Pitris S, Alexoudi T, et al. 4-channel 200 Gb/s WDM O-band silicon photonic transceiver sub-assembly. Optics Express, 2020, 28(4), 5706 doi: 10.1364/OE.373454
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    Received: 25 May 2024 Revised: Online: Uncorrected proof: 27 May 2024Published: 15 July 2024

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      Ang Li, Qianli Ma, Yujun Xie, Yongliang Xiong, Yingjie Ma, Han Liu, Ye Jin, Menghan Yang, Guike Li, Haoran Yin, Minye Zhu, Yang Qu, Peng Wang, Daofa Wang, Wei Li, Liyuan Liu, Nan Qi, Ming Li. A 256 Gb/s electronic−photonic monolithically integrated transceiver in 45 nm CMOS[J]. Journal of Semiconductors, 2024, 45(7): 070501. doi: 10.1088/1674-4926/24050040 A Li, Q L Ma, Y J Xie, Y L Xiong, Y J Ma, H Liu, Y Jin, M H Yang, G K Li, H R Yin, M Y Zhu, Y Qu, P Wang, D F Wang, W Li, L Y Liu, N Qi, and M Li, A 256 Gb/s electronic−photonic monolithically integrated transceiver in 45 nm CMOS[J]. J. Semicond., 2024, 45(7), 070501 doi: 10.1088/1674-4926/24050040Export: BibTex EndNote
      Citation:
      Ang Li, Qianli Ma, Yujun Xie, Yongliang Xiong, Yingjie Ma, Han Liu, Ye Jin, Menghan Yang, Guike Li, Haoran Yin, Minye Zhu, Yang Qu, Peng Wang, Daofa Wang, Wei Li, Liyuan Liu, Nan Qi, Ming Li. A 256 Gb/s electronic−photonic monolithically integrated transceiver in 45 nm CMOS[J]. Journal of Semiconductors, 2024, 45(7): 070501. doi: 10.1088/1674-4926/24050040

      A Li, Q L Ma, Y J Xie, Y L Xiong, Y J Ma, H Liu, Y Jin, M H Yang, G K Li, H R Yin, M Y Zhu, Y Qu, P Wang, D F Wang, W Li, L Y Liu, N Qi, and M Li, A 256 Gb/s electronic−photonic monolithically integrated transceiver in 45 nm CMOS[J]. J. Semicond., 2024, 45(7), 070501 doi: 10.1088/1674-4926/24050040
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      A 256 Gb/s electronic−photonic monolithically integrated transceiver in 45 nm CMOS

      doi: 10.1088/1674-4926/24050040
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      • Ang Li is a PhD candidate in the University of Chinese Academy of Sciences, Beijing, China. He received his Bachelor degree from Beijing University of Posts and Telecommunications in 2021. His current research interests include high speed optoelectronic device and optoelectronic integration based on silicon photonics
      • Qianli Ma received his B.S degree in electronic information of engineering from the University of Chinese Academy of Sciences, Beijing, China, in 2021. He is currently a master student in the Institute of Semiconductors, Chinese Academy of Sciences. His current research interests include optical transceiver circuits and high frequency clock generation
      • Yujun Xie received the B.S. degree in electrical engineering and automation from the Fudan University, Shanghai, China, in 2016, and the Ph.D. degree in physical electronics from Fudan University in 2021. He currently holds a post-doctoral position with the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China. His research interests include high-speed optoelectronic materials and devices
      • Nan Qi (M’13) received the B.S. degree from Beijing Institute of Technology, Beijing, China, in 2005, the M.S. and Ph.D. degrees from Tsinghua University, Beijing, China, in 2008 and 2013 respectively. From 2013 to 2015, he was a Research Scholar with the Department of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, USA. From 2015 to 2017, he was a Visiting Scholar and then a Circuit-Design Engineer at Hewlett-Packard Labs, Palo Alto, CA, USA. In 2017, he joined the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China, where he is now a full professor on electronic circuits and systems. His research interests include the design of integrated circuits for high-speed wireline/optical and wireless transceivers
      • Ming Li received the Ph.D. degree in electrical and electronics engineering from the University of Shizuoka, Hamamatsu, Japan, in 2009. In 2009, he was with the Microwave Photonics Research Laboratory, School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, ON, Canada, as a Postdoctoral Research Fellow. In 2011, he was with the Ultrafast Optical Processing Group under the supervision of INRS-EMT, Montreal, QC, Canada, as a Postdoctoral Research Fellow. In 2013, he was with the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China, as a Full Professor under the support of Thousand Youth Talents Program. He has authored more than 140 high-impact journal papers. His research interests include integrated microwave photonics and its applications, ultrafast optical signal processing, and high-speed real-time optical measurement and sensing
      • Corresponding author: qinan@semi.ac.cnml@semi.ac.cn
      • Received Date: 2024-05-25
        Available Online: 2024-05-27

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