| Citation: |
DAI Hong-yu, ZHANG Sheng, ZHOU Run-de. Power Optimization Methods of Energy Recovery Circuits[J]. Journal of Semiconductors, 2002, In Press.
. Power Optimization Methods of Energy Recovery Circuits[J]. J. Semicond, 2002, In Press.
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Power Optimization Methods of Energy Recovery Circuits
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Abstract
The non adiabatic loss in energy recovery circuit is proportional to CLΔV2. Two methods are presented to lower the two factors of CL and ΔV. High efficient energy recovery logic (HEERL) circuit utilizes bootstrap effect to decrease node residential voltage ΔV. Improved energy recovery logic (IERL) adds extra recovery path to improve the recovery efficiency. At the same time the control node has CAΔV2 non adiabatic loss, but the total circuit power is saved. Compared with other energy recovery circuits, the two circuits presented show more than 50% power saving with only small area loss.
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Keywords:
- energy recovery,
- low power,
- adiabatic computation,
- CMOS circuit
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References
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Proportional views
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