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• ## Optimization of erase time degradation in 65 nm NOR flash memory chips

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Reliability issues of flash memory are becoming increasingly significant with the shrinking of technology nodes. Among them, erase time degradation is an issue that draws the attention of academic and industry researchers. In this paper, causes of the " erase time degradation” are exhaustively analyzed, with proposals for its improvement presented, including a low stress program/erase scheme with a staircase pulse and disturb-immune array bias condition. Implementation of the optimized circuit structure is verified in a 128 Mb SPI NOR Flash memory chip, which is fabricated on a SMIC 65 nm ETOX process platform. Testing results indicate a degradation of the sector erase time from 10.67 to 104.9 ms after 105 program/erase cycles, which exhibits an improvement of approximately 100 ms over conventional schemes.

• ## Performance improvement of light-emitting diodes with double superlattices confinement layer

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In this study, the effect of double superlattices on GaN-based blue light-emitting diodes (LEDs) is analyzed numerically. One of the superlattices is composed of InGaN/GaN, which is designed before the multiple quantum wells (MQWs). The other one is AlInGaN/AlGaN, which is inserted between the last QB (quantum barriers) and p-GaN. The crucial characteristics of Double Superlattices LEDs structure, including the energy band diagrams, carrier concentrations in the active region, light output power, internal quantum efficiency, respectively, were analyzed in detail. The simulation results suggest that compared with the conventional AlGaN electron-blocking layer (EBL) LED, the LED with double superlattices has better performance due to the enhancement of electron confinement and the increase of hole injection. The double superlattices can make it easier for the carriers tunneling to the MQWs, especially for the holes. Furthermore, the LED with the double superlattices can effectively suppress the electron overflow out of multiple quantum wells simultaneously. From the result, we argue that output power is enhanced dramatically, and the efficiency droop is substantially mitigated when the double superlattices are used.

• ## Electrical properties of Si/Si bonded wafers based on an amorphous Ge interlayer

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An amorphous Ge (a-Ge) intermediate layer is introduced into the Si bonded interface to lower the annealing temperature and achieve good electrical characteristics. The interface and electrical characteristics of n-Si/n-Si and p-Si/n-Si junctions manufactured by low-temperature wafer bonding based on a thin amorphous Ge are investigated. It is found that the bubble density tremendously decreases when the a-Ge film is not immersed in DI water. This is due to the decrease of the –OH groups. In addition, when the samples are annealed at 400 °C for 20 h, the bubbles totally disappear. This can be explained by the appearance of the polycrystalline Ge (absorption of H2) at the bonded interface. The junction resistance of the n-Si/n-Si bonded wafers decreases with the increase of the annealing temperature. This is consistent with the recrystallization of the a-Ge when high-temperature annealing is conducted. The carrier transport of the Si-based PN junction annealed at 350 °C is consistent with the trap-assisted tunneling model and that annealed at 400 °C is related to the carrier recombination model.

• ## Berger code based concurrent online self-testing of embedded processors

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In this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable methodology is proposed and integrated in 32-bit DLX reduced instruction set computer (RISC) processor on a single silicon chip. The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self-testing to detect temporary faults.

• ## The developing condition analysis of semiconductor laser frequency stabilization technology

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The frequency stability of free-running semiconductor lasers is influenced by several factors, such as driving current and external operating environment. The frequency stabilization of laser has become an international research hotspot in recent years. This paper reviews active frequency stabilization technologies of laser diodes and elaborates their principles. Based on differences of frequency discrimination curves, these active frequency stabilization technologies are classified into three major types, which are harmonic frequency stabilization, Pound-Drever-Hall (PDH) technology and curve subtraction frequency stabilization. Further, merits and demerits of each technology are compared from aspects of frequency stability and structure complexity. Finally, prospects of frequency stabilization technologies of semiconductor lasers are discussed in detail. Combining several of these methods are future trends, especially the combination of frequency stabilization of F–P cavity. And PID electronic control for optimizing the servo system is generally added in the methods mentioned above.

• ## Impact of damping on high speed 850 nm VCSEL performance

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High speed VCSELs are important optical devices in short-reach optical communication links and interconnects because of their low cost and high modulation speeds. In this paper, the impact of damping on the VCSELs’ static and dynamic characteristic is analyzed and demonstrated. Through the shallow corrosion of the top layer DBR, the VCSELs with different damping is designed and fabricated. With the increase of the surface etch depth from 0 to ~55 nm for 9 μm oxide-aperture VCSEL, the K factor related with the damping is reduced from 0.31 to 0.23 ns−1. When the etch depth of the VCSEL with 9 μm oxide-aperture is decreased to ~25 nm, output power is increased from 4.03 to 4.70 mW and small signal modulation bandwidth is also increased from 15.46 to 16.37 GHz. It shows that there is a tradeoff between damping and differential gain for improving modulation speed.

• ## A high-efficiency charge pump in BCD process for implantable medical devices

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This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS (BCD) technology for implantable medical devices. Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm2.

• ## FEM thermal analysis of high power GaN-on-diamond HEMTs

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A three-dimensional thermal analysis of GaN HEMTs on diamond substrate is investigated using the finite element method. The diamond substrate thickness, area and shape, transition layer thickness and thermal conductivity of the transition layer are considered and treated appropriately in the numerical simulation. The temperature distribution and heat spreading paths are investigated under different conditions and the results indicate that the existence of the transition layer causes an increase in the channel temperature and the thickness, area and shape of the diamond substrate have certain impacts on the channel temperature too. Channel temperature reduces with increasing diamond substrate thickness and area but with a decreasing trend, which can be explained by the saturation effects of the diamond substrate. The shape of diamond substrate also affects the temperature performance of GaN HEMTs, therefore, to achieve a favorable heat dissipation effect with the settled diamond substrate area, the shape should contain as many isothermal curves as possible when the isothermal gradient is constant. The study of the thermal properties of GaN on diamond substrate is useful for the prediction of heating of high power GaN HEMTs devices and optimal designs of an efficient heat spreader for GaN HEMTs.

• ## A 0.9 V PSRR improved voltage reference using a wide-band cascaded current mode differentiator

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We present a voltage reference using a wide-band cascaded current mode differentiator, for the improved PSRR performance. Compared with the conventional references, the reference with the technique is mainly characterized by a two cascaded stages current mode signal differentiator. In the differentiator, a zero OTA Gm is proposed, to achieve the wide-band differential characteristic. With the technique, the PSRR beyond the pole’s corresponding frequency can be significantly improved with the minimum supply voltage only about VGS_PMOS + (VGS_NMOSVTH). Fabricated with a 0.18 μm CMOS process, with the 0.9 V supply voltage, the PSRR @ 20 MHz of the reference is achieved at −54 dB. Moreover, the power dissipation is 19 μW.

• ## Research progress and challenges of two dimensional MoS2 field effect transistors

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This review paper gives an outline of the recent research progress and challenges of 2D TMDs material MoS2 based device, that leads to an interesting path towards approaching the electronic applications due to its sizeable band gap. This review presents the improvement of MoS2 material as an alternate to a silicon channel in a transistor with its excellent energy band gap, thermal conductivity, and exclusive physical properties that are expected to draw attention to focusing on semiconducting devices for most futuristic applications. We discuss the band structure of MoS2 for a different number of layers with its structure, and various synthesis techniques of the MoS2 layer are also reviewed. The MoS2 based field effect transistor has attracted a great deal of attention due to its excellent properties such as mobility, on/off current ratio, and maximum on-current of the devices. The transition of mobility as a function of temperature and thickness dependence are also discussed. However, the mobility of MoS2 material is large in bulk form and lower in monolayer form. The use of a high-k gate dielectric in MoS2 FET is used to enhance the mobility of the device. Different metal contact engineering and different doping techniques were deployed to achieve low contact resistance. This review paper focuses on various aspects of layered TMDs material MoS2 based field effect transistors.

• ## Ultralow specific ON-resistance high-k LDMOS with vertical field plate

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An ultralow specific on-resistance high-k LDMOS with vertical field plate (VFP HK LDMOS) is proposed in this paper. The high-k dielectric trench and highly doped interface N+ layer are made in bulk silicon to reduce the surface field of the drift region in the VFP HK LDMOS. The gate vertical field plate (VFP) pinning in the high-k dielectric trench can modulate the bulk electric field. The high-k dielectric not only provides polarized charges to assist depletion of the drift region, so that the drift region and high-k trench maintain charge balance adaptively, but also can fully assist in depleting the drift region to increase the drift doping concentration and reshape the electric field to avoid premature breakdown. Compared with the conventional structure, the VFP HK LDMOS has the breakdown voltage of 629.1 V at the drift length of 40 μm and the specific on-resistance of 38.4 mΩ·cm2 at the gate potential of 15 V. Then the power figure of merit is 10.31 MW/cm2.

• ## High order DBR GaSb based single longitude mode diode lasers at 2 μm wavelength

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The GaSb-based distributed Bragg reflection (DBR) diode laser with 23rd-order gratings have been fabricated by conventional UV lithography and inductively coupled plasma (ICP) etching. The ICP etching conditions were optimized and the relationship among etching depth, duty ratio and side-mode suppression ratio (SMSR) was studied. The device with a ridge width of 100 μm, gratings period of 13 μm and etching depth of 1.55 μm as well as the duty ratio of 85% was fabricated, its maximum SMSR reached 22.52 dB with uncoated cavity facets under single longitudinal operation mode at room temperature.

• ## Modeling of tunneling current density of GeC based double barrier multiple quantum well resonant tunneling diode

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In this paper, the double barrier quantum well (DBQW) resonant tunneling diode (RTD) structure made of SiGeSn/GeC/SiGeSn alloys grown on Ge substrate is analyzed. The tensile strained Ge1−zCz on Si1−xyGexSny heterostructure provides a direct band gap type I configuration. The transmission coefficient and tunneling current density have been calculated considering single and multiple quantum wells. A comparative study of tunnelling current of the proposed structure is done with the existing RTD structure based on GeSn/SiGeSn DBH. A higher value of the current density for the proposed structure has been obtained.

• ## Reliability testing of a 3D encapsulated VHF MEMS resonator

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The frequency stability of a three-dimensional (3D) vacuum encapsulated very high frequency (VHF) disk resonator is systematically investigated. For eliminating the parasitic effect caused by the parasitic capacitance of the printed circuit board (PCB), a negating capacitive compensation method was developed. The testing results implemented at 25 °C for 240 h for the long-term stability indicates that the resonant frequency variation remained within ±1 ppm and the noise floor derived from Allan Deviation was 26 ppb, which is competitive with the conventional quartz resonators. The resonant frequency fluctuation of 1.5 ppm was obtained during 200 temperature cycling between −40 and 85 °C.

• ## Impact of varying carbon concentration in SiC S/D asymmetric dual-k spacer for high performance and reliable FinFET

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In this paper, we propose a reliable asymmetric dual-k spacer with SiC source/drain (S/D) pocket as a stressor for a Si channel. This enhances the device performance in terms of electron mobility (eMobility), current driving capabilities, transconductance (Gm) and subthreshold slope (SS). The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance. We analysed the variation in drive current for different values of carbon (C) mole fraction y in Si1−yCy. It is found that the mole fraction also helps to improve device lifetime, performance enhancement also pointed by transconductance variation with the gate length. All the simulations are performed in the 3-D Sentaurus TCAD tool. The proposed device structure achieved ION = 2.17 mA/μm for Si0.3C0.7 and found that Si0.5C0.5 is more suitable for the perspective of a process variation effect for 14 nm as the gate length. We introduce reliability issues and their solutions for Si1−yCy FinFET for the first time.

• ## High-performance pulse-width modulation AC/DC controller using novel under voltage lockout circuit according to Energy Star VI standard

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This paper proposes a high-performance pulse-width modulation (PWM) AC/DC controller, which can drive a high-voltage (HV) 650-V power metal-oxide-semiconductor field-effect Transistor (MOSFET) in typical applications of adapters in portable electronic devices. In order to reduce the standby power consumption and improve the response speed in the start-up state, an improved under voltage lockout (UVLO) circuit without a voltage reference source or comparator is adopted. The AC/DC controller is fabricated using a 40-V 0.8-μm one-poly two-metal (1P2M) CMOS process, and it only occupies 1410 × 730 μm2. A 12 V/2 A flyback topology for quick-charge application is illustrated as the test circuit, which is currently one of the most advanced power adapters in use. Test values show that the turn-on and the turn-off threshold voltages are 19.318 and 8.01 V, respectively. A high hysteresis voltage of 11.308 V causes the value of the power-charging capacitor to decrease to as low as 1 μF to reduce production cost. In addition, the start-up current of 2.3 μA is extremely small, and is attributed to a reduction in the system's standby power consumption. The final test results of the overall system are proven to meet the Energy Star VI standard. The controller has already been mass produced for industrial applications.

• ## Two dimensional analytical model for a negative capacitance double gate tunnel field effect transistor with ferroelectric gate dielectric

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Analytical models are presented for a negative capacitance double-gate tunnel field-effect transistor (NC DG TFET) with a ferroelectric gate dielectric in this paper. The model accurately calculates the channel potential profile by solving the Poisson equation with the Landau–Khalatnikov (LK) equation. Moreover, the effects of the channel mobile charges on the potential are also taken into account. We also analyze the dependences of the channel potential and the on-state current on the device parameters by changing the thickness of ferroelectric layer, ferroelectric material and also verify the simulation results accord with commercial TCAD. The results show that the device can obtain better characteristics when the thickness of the ferroelectric layer is larger as it can reduce the shortest tunneling length.

• ## Synthesis and characterization of poly (2,5-diyl pyrrole-2-pyrrolyl methine) semiconductor copolymer

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In the current research, the proposed technique to synthesise poly {(2,5-diyl pyrrole) (2-pyrrolyl methine)} (PPPM) copolymer by condensation of pyrrole and pyrrole-2- carboxaldehyde monomers catalyzed by Maghnite-H+ is introduced. The protons are exchanged with Maghnite-H+, which is available in the form of a montmorillonite silicate clay sheet. The effect of several parameters such as time and temperature of copolymerization, [pyrrole]/[pyrrole-2-carboxaldehyde] molar ratio, amount of Maghnite-H+, and solvent on the produced poly (2,5-diyl pyrrole-2- pyrrolyl methine) semiconductor copolymer material (yield%) was investigated. The synthesized PPPM copolymer was characterized using nuclear magnetic resonance, Fourier transform infrared, and ultraviolet-visible spectroscopy. The results show that the synthesized copolymer using the copolymerization technique is a real organic copolymer consisting of two monomers units (i.e, pyrrole and pyrrole- 2-carboxaldehyde). Also, the synthesized copolymer is more soluble than polypyrrole in most of the commonly used organic solvents. Hence, copolymerization of pyrrole with pyrrole-2- carboxaldehyde will overcome the insolubility of polypyrrole. In addition, the resultant copolymer exhibits good film formability. The produced copolymer has several potential applications in the field of rechargeable batteries, sensors, capacitors, light emitting diodes, optical displays, and solar cells.

• ## Influence of channel/back-barrier thickness on the breakdown of AlGaN/GaN MIS-HEMTs

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The leakage current and breakdown voltage of AlGaN/GaN/AlGaN high electron mobility transistors on silicon with different GaN channel thicknesses were investigated. The results showed that a thin GaN channel was beneficial for obtaining a high breakdown voltage, based on the leakage current path and the acceptor traps in the AlGaN back-barrier. The breakdown voltage of the device with an 800 nm-thick GaN channel was 926 V @ 1 mA/mm, and the leakage current increased slowly between 300 and 800 V. Besides, the raising conduction band edge of the GaN channel by the AlGaN back-barrier lead to little degradation for sheet 2-D electron gas density, especially, in the thin GaN channel. The transfer and output characteristics were not obviously deteriorated for the samples with different GaN channel thickness. Through optimizing the GaN channel thickness and designing the AlGaN back-barrier, the lower leakage current and higher breakdown voltage would be possible.

• ## Theoretical simulation of T2SLs InAs/GaSb cascade photodetector for HOT condition

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The investigation of the interband type-II superlattice InAs/GaSb cascade photodetector in the temperature range of 320–380 K is presented in this paper. The article is devoted to the theoretical modeling of the cascade detector characteristics by the use of the SimuApsys platform and the 4-band model (kp 8 × 8 method). The obtained theoretical characteristics are comparable with experimentally measured ones, suggesting that transport in the absorber is determined by the dynamics of intrinsic carriers and by their lifetime. An overlap equal to 120 meV was used in calculations and a correction term in the " non-common atom” model Hxy = 700 meV was added to the Hamiltonian. The electron and hole effective masses from dispersion curves were estimated and absorption coefficient α was calculated. Based on the simulation detectivity, D* characteristics in the temperature range 320–380 K were calculated. The simulated theoretical characteristics at 320 K are comparable to experimentally measured ones, however at higher temperatures, the experimental value of D* does not reach the theoretical values due to the low resistance of the device and short diffusion length.

• ## Impact of ambient temperature on the self-heating effects in FinFETs

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We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect (SHE) in 14 nm bulk nFinFETs with ambient temperature (TA) from 220 to 400 K. Based on this method, non-local heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/SiO2 are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) not all input power (Qinput) turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport; (ii) a higher TA leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages; (iii) SHE can lead to serious degradation in the carrier transport, which will increase when TA increases; (iv) the current degradation can be 8.9% when Vds = 0.7 V, Vgs = 1 V and TA = 400 K; (v) device thermal resistance (Rth) increases with increasing of TA, which is seriously impacted by the non-equilibrium transport. Hence, the impact of TA should be carefully considered when investigating SHE in nanoscale devices.

• ## A 0.19 ppm/°C bandgap reference circuit with high-PSRR

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A high-order curvature-compensated CMOS bandgap reference (BGR) topology with a low temperature coefficient (TC) over a wide temperature range and a high power supply reject ratio (PSRR) is presented in this paper. High-order correction is realized by incorporating a nonlinear current INL, which is generated by ∆VGS across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of 0.19 ppm/°C over the temperature range of 165 °C (−40 to 125 °C), PSRR of −123 dB @ DC and −56 dB @ 100 kHz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.

• ## Multivariate rational regression and its application in semiconductor device modeling

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Physics equation-based semiconductor device modeling is accurate but time and money consuming. The need for studying new material and devices is increasing so that there has to be an efficient and accurate device modeling method. In this paper, two methods based on multivariate rational regression (MRR) for device modeling are proposed. They are single-pole MRR and double-pole MRR. The two MRR methods are proved to be powerful in nonlinear curve fitting and have good numerical stability. Two methods are compared with OLS and LASSO by fitting the SMIC 40 nm MOS-FET I–V characteristic curve and the normalized mean square error of Single-pole MRR is \begin{document}$3.02 \times {10^{{\rm{ - }}8}}$\end{document} which is 4 magnitudes less than an ordinary least square. The I–V characteristics of CNT-FET and performance indicators (noise factor, gain, power) of a low noise amplifier are also modeled by using MRR methods. The results show MRR methods are very powerful methods for semiconductor device modeling and have a strong nonlinear curve fitting ability.

• ## An improved SOI trench LDMOST with double vertical high-k insulator pillars

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An SOI trench LDMOST (TLDMOST) with ultra-low specific on-resistance (Ron,sp) is proposed. It features double vertical high-k insulator pillars (Hk1 and Hk2) in the oxide trench, which are connected to the source electrode and drain electrode, respectively. Firstly, under reverse bias voltage, most electric displacement lines produced by the charges of the depleted drift region in the source side go through the Hk1, and thus the average electric field strength under the source can be enhanced. Secondly, two additional electric field peaks are induced by the Hk1, which further modulate the electric field in the drift region under the source. Thirdly, most electric displacement lines produced by the charges of the depleted drift region in the drain side enter into the Hk2. This not only introduces one more electric field peak at the corner of the oxide trench around the Hk2, but also forms the enhanced vertical reduced surface field effect, which modulates the electric field in the drift region under the drain. With the effects of the two Hk insulator pillars, the breakdown voltage (BV) and the drift region doping concentration are significantly improved. The simulation results indicate that compared with the oxide trench LDMOST (previous TLDMOST) with the same geometry, the proposed double Hk TLDMOST enhances the BV by 86% and reduces the Ron,sp by 88%.

• ## Low voltage floating gate MOSFET based current differencing transconductance amplifier and its applications

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This article presents a low voltage low power configuration of current differencing transconductance amplifier (CDTA) based on floating gate MOSFET. The proposed CDTA variant operates at lower supply voltage ±1.4 V with total static power dissipation of 2.60 mW due to the low voltage feature of floating gate MOSFET. High transconductance up to 6.21 mA/V is achieved with extended linear range of the circuit i.e. ±130 μA. Two applications are illustrated to demonstrate the effectiveness of the proposed active block. A quadrature oscillator is realized using FGMOS based CDTA, two capacitors, and a resistor. The resistor is implemented using two NMOSFETs to provide high linearity and tunablility. Another application is the Schmitt trigger circuit based on the proposed CDTA variant. All circuits are simulated by using SPICE and TSMC 130 nm technology.

• ## An empirical method for improving accuracy of human eye temperature measured by uncooled infrared thermal imager

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In order to reduce the temperature measurement error with the uncooled infrared thermal imager, experiments were conducted to evaluate the effects of environment temperature and measurement distance on the measurement error of human eye temperature. First, the forehead temperature was used as an intermediate variable to obtain the actual temperature of human eyes. Then, the effects of environment temperature and measurement distance on the temperature measurement were separately analyzed. Finally, an empirical model was established to correlate actual eye temperature with the measured temperature, environment temperature, and measurement distance. To verify the formula, three different environment temperatures were tested at different distances. The measurement errors were substantially reduced using the empirical model for temperature correction. The results show that this method can effectively improve the accuracy of temperature measurement using the infrared thermal imager.

• ## Elaboration of ZnO nanowires by solution based method, characterization and solar cell applications

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ZnO nanowires (NWs) layers have been synthesized using a two-step chemical solution method on ITO glass substrates coated with ZnO seeds at different immersing times. The structures, morphology and optical properties of the synthesized ZnO NWs have been investigated. The prepared ZnO NWs have an obvious polycrystalline hexangular wurtzite structure and are preferentially oriented along the c-axis (002). FESEM micrographs showed that the prepared ZnO NWs are close to being vertically grown and more densely at higher immersing times. Poly [2-methoxy-5(2′-ethyl-hexyloxy)-1,4-phenylenevinylene], MEH-PPV, was used as an active layer to prepare three samples of MEH-PPV/ZnO solar cell based on ZnO NWs that were prepared at different immersing times. A maximum power conversion efficiency of 0.812% was achieved for MEH-PPV/ZnO solar cell prepared at a higher immersing time. The improved efficiency may be attributed to the enhancement of both open-circuit voltage and fill factor.

• ## Coeffect of trapping behaviors on the performance of GaN-based devices

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Trap-induced current collapse has become one of the critical issues hindering the improvement of GaN-based microwave power devices. It is difficult to study the behavior of each trapping effect separately with the experimental measurement. Transient simulation is a useful technique for analyzing the mechanism of current collapse. In this paper, the coeffect of surface- and bulk-trapping behaviors on the performance of AlGaN/GaN HEMTs is investigated based on the two-dimensional (2D) transient simulation. In addition, the mechanism of trapping effects is analyzed from the aspect of device physics. Two simulation models with different types of traps are used for comparison, and the simulated results reproduced the experimental measured data. It is found that the final steady-state current decreases when both the surface and bulk traps are taken into account in the model. However, contrary to the expectation, the total current collapse is dramatically reduced (e.g. from 18% to 4% for the 90 nm gate-length device). The results suggest that the surface-related current collapse of GaN-based HEMTs may be mitigated in some degree due to the participation of bulk traps with short time constant. The work in this paper will be helpful for further optimization design of material and device structures.

• ## Solution flow rate influence on ZnS thin films properties grown by ultrasonic spray for optoelectronic application

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The aim of this work is to investigate the dependence of ZnS thin films structural and optical properties with the solution flow rate during the deposition using an ultrasonic spray method. The solution flow rate ranged from 10 to 50 mL/h and the substrate temperature was maintained at 450 °C. The effect of the solution flow rate on the properties of ZnS thin films was investigated by X-ray diffraction (XRD), scanning electron microscopy (SEM), optical transmittance spectroscopy (UV–V) and the four-point method. The X-ray diffraction analysis showed that the deposited material was pure zinc sulphide, it has a cubic sphalerite structure with preferential orientation along the (111) direction. The grain size values were calculated and found to be between 38 to 82 nm. SEM analysis revealed that the deposited thin films have good adherence to the substrate surfaces, are homogeneous and have high density. The average transmission of all films is up more than 65% in the range wavelength from 200 to 1100 nm and their band gap energy values were found between 3.5–3.92 eV. The obtained film thickness varies from 390 to 1040 nm. Moreover, the electric resistivity of the deposited films increases with the increasing of the solution flow rate between 3.51 × 105 and 11 × 105 Ω·cm.

• ## Characterizations of high-voltage vertically-stacked GaAs laser power converter

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Six-junction vertically-stacked GaAs laser power converters (LPCs) with n+-GaAs/p+-Al0.37Ga0.63As tunnel junctions have been designed and grown by metal-organic chemical vapor deposition for converting the power of 808 nm lasers. The LPC chips are characterized by measuring current–voltage (I–V) characteristics under 808 nm laser illumination, and a maximum conversion efficiency ηc of 53.1% is obtained for LPCs with an aperture diameter of 2 mm at an input laser power of 0.5 W. In addition, the characteristics of the LPCs are analyzed by a standard equivalent-circuit model, and the reverse saturation current, ideality factor, series resistance and shunt resistance are extracted by fitting of the I–V curves.

• ## The influence of pulsed parameters on the damage of a Darlington transistor

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In this paper, theoretical research on the heat accumulation effect of a Darlington transistor induced by high power microwave is conducted, and temperature variation as functions of pulse repetitive frequency (PRF) and duty cycle (DC) are studied. According to the distribution of the electronic field and the current density in the Darlington transistor, the research of the damage mechanism is carried out. The results show that for repetitive pulses with the same pulse widths and different PRFs, the value of temperature variation increases with PRF increases, and the peak temperature has almost no change when PRF is lower than 200 kHz; while for the repetitive pulses with the same PRF and different pulse widths, the larger the pulse width is, the greater temperature variation varies. The response of the peak temperature caused by a single pulse demonstrates that there is no temperature variation when the rising time is much shorter than the falling time. In addition, the relationship between the temperature variation and the time during the rising edge time as well as that between the temperature variation and the time during the falling edge time are obtained utilizing the curve fitting method. Finally, for a certain average power, with DC increases the value of temperature variation decreases.

• ## Effect of single walled carbon nanotubes on series resistance of Rose Bengal and Methyl Red dye-based organic photovoltaic device

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In this paper, the influence of single walled carbon nanotube (SWCNT) on the series resistance (Rs) of Rose Bengal (RB) and Methyl Red (MR) dye-based organic diodes has been studied. It has been revealed from experimental results that SWCNT has a significant effect on Rs. The values of Rs are measured from current–voltage (I–V) characteristics and also by utilizing the Cheung method. Obtained values from the Cheung method have been verified using H(I)–I plots for all dye-based devices. The extracted values using these two processes show a good consistency with each other. It is observed that Rs is reduced significantly by incorporating SWCNT for both dyes. The estimated amounts of reduction of Rs using SWCNT are 76.08% and 64.23% obtained from the IV relationship whereas the value of Rs shows a reduction of 83.5% and 67.1% when measured by using the Cheung method for RB and MR dyes respectively. The ideality factor and barrier height of the diodes have also been extracted. The ideality factor has decreased with incorporation of SWCNT. A reduction in barrier height for the devices has also been observed in the presence of SWCNT.

• ## Steady state electrical–thermal coupling analysis of TSV

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This paper presents a blended analytical electrical–thermal model for steady state thermal analysis of through-silicon-via (TSV) in three-dimensional (3D) integrated circuits. The proposed analytical model is validated by the commercial FEM tool—COMSOL. The comparison between the results of the proposed analytical formulas and COMSOL shows that the proposed formulas have very high accuracy with a maximum error of 0.1%. Based on the analytical model, the temperature performance of TSV is studied. Design guide lines of TSV are also given as: (1) the radius of the TSV increases, the resistance decreases and the temperature can be increased; (2) the thicker the dielectric layer, the higher the temperature; (3) compared with carbon nanotube, the Cu enlarges the temperature by 34 K, and the W case enlarges the temperature by 41 K.

• ## Supplementary information

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• ## Dynamic nuclear self-polarization of III–V semiconductors

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doi: 10.1088/1674-4926/39/8/082001

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III–V semiconductors exhibit dynamic nuclear self-polarization (DYNASP) owing to the contact hyperfine interaction (HFI) between optically excited conduction electrons and lattice nuclei. In the self-polarization process at a low temperature, electron spin state and the nuclear polarization (magnetization) exchange a positive feedback, increasing energy splitting of the conduction electron states, thereby a large nuclear polarization. This phenomenon was theoretically predicted previously for conduction electrons excited linearly and elliptically polarized light. The polarization of the conduction electrons was represented by a parameterα in a formula for nuclear polarization (Eq. (9) in Ref. [1]); however, the effect of external magnetic fields on the nuclear polarization was not considered. Therefore, this study introduces this effect by further extending the previous studies. Herein, α′ represents the combination of the effects of elliptically polarized electrons and an external magnetic field, which is used in the equations presented in previous studies. When α′ = 0, a large nuclear polarization is obtained below critical temperature Tc, but no polarization occurs above Tc. When α′ > 0, the nuclear polarization is enhanced above Tc. Below Tc, the nuclear polarization follows a hysteresis curve when α′ is partially manipulated by adjusting the degree of the polarization of the exciting laser.

• ## The effect of parasitic charge on the output stability of MEMS gyroscopes

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doi: 10.1088/1674-4926/39/8/084002

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Output voltage drifting was observed in MEMS gyroscopes. Other than the quadrature error, frequency mismatch and quality factor, the dielectric parasitic charge was thought to be a major determinant. We studied the mechanism and variation of the parasitic charge in the MEMS gyroscopes, and analyzed the effect of the parasitic charge on the output stability. This phenomenon was extremely obvious in the Pyrex encapsulated MEMS gyroscopes. Due to the DC voltage required for the electrostatic actuation, the parasitic charge in the dielectric layer would accumulate and induce a residual voltage. This voltage had an impact on the resonant frequency of the gyroscopes, so as to affect the output stability. The theoretical studies were also confirmed by our experimental results. It was shown that the parasitic charge was harmful to the output stability of MEMS gyroscopes.

• ## Collaborative R&D between multicrystalline silicon ingots and battery efficiency improvement—effect of shadow area in multicrystalline silicon ingots on cell efficiency

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doi: 10.1088/1674-4926/39/8/083004

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We characterized strip-like shadows in cast multicrystalline silicon (mc-Si) ingots. Blocks and wafers were analyzed using scanning infrared microscopy, photoluminescence spectroscopy, laser scanning confocal microscopy, field-emission scanning electron microscopy, X-ray energy-dispersive spectrometry, and microwave photoconductivity decay technique. The effect on solar cell performance is discussed. The results show that the non-microcrystalline shadow region in Si ingots consists of precipitates of Fe, O, and C. The size of these Fe–O–C precipitates found at the shadow region is ~25 μm. Fe–O–C impurities can slightly reduce the minority carrier lifetime of the wafers while severely decrease in shunt resistance, leading to the increase in reverse current of the solar cells and degradation in cell efficiency.

• ## Hybrid AlGaInAs/Si Fabry–Pérot lasers with near-total mode confinements

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doi: 10.1088/1674-4926/39/8/084001

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We have proposed and demonstrated hybrid AlGaInAs/Si Fabry–Pérot (FP) lasers, with the FP cavity facet covered by the p-electrode metal for enhancing mode confinement. Continuous-wave lasing is obtained at room temperature with a threshold current of 45 mA for the hybrid FP laser with a cavity length of 415 μm and a width of 7 μm. Near-field optical microscope images indicate an efficient output emission from the underneath evanescently-coupled silicon waveguide. Furthermore, single-mode lasing with a side-mode suppression-ratio of 29 dB and a threshold current of 16 mA is realized for the 150 μm-long hybrid FP laser.

• ## Growth and characterization of 2-inch high quality β-Ga2O3 single crystals grown by EFG method

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doi: 10.1088/1674-4926/39/8/083003

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β-Ga2O3 is an ultra-wide band-gap semiconductor with promising applications in UV optical detectors, Schottky barrier diodes, field-effect transistors and substrates for light-emitting diodes. However, the preparation of large β-Ga2O3 crystals is undeveloped and many properties of this material have not been discovered yet. In this work, 2-inch β-Ga2O3 single crystals were grown by using an edge-defined film-fed growth method. The high quality of the crystal has been proved by high-resolution X-ray diffraction with 19.06 arcsec of the full width at half maximum. The electrical properties and optical properties of both the unintentionally doped and Si-doped β-Ga2O3 crystals were investigated systematically.

• ## Room-temperature optically pumped InAs/GaAs quantum dots microdisk lasers on SiO2/Si chip

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doi: 10.1088/1674-4926/39/8/084003

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We report on room temperature continuous-wave optically pumped InAs/GaAs quantum dot whispering gallery mode microdisk lasers, heterogeneously integrated on silica/silicon chips. The microdisks are fabricated by photolithography and inductively coupled plasma etching. The lasing wavelength is approximately 1200 nm and the obtained lowest laser threshold is approximately 28 μW. The experimental results show an approach of possible integrated III–V optical active materials on silica/silicon chip for low threshold WGM microdisk lasers.

• ## A low standby-power fast carbon nanotube ternary SRAM cell with improved stability

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doi: 10.1088/1674-4926/39/8/085002

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Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors (CNFETs). The performance is simulated in terms of three criteria including standby-power, delay (write and read) and stability (RSNM). Compared to the novel ternary SRAM cell, our results show that the average standby-power, write and read delay of the proposed cell are reduced by 78.1%, 39.6% and 58.2%, respectively. In addition, the RSNM under process variations is 2.01× and 1.95× of the conventional and novel ternary SRAM cells, respectively.

• ## Photoluminescence and structural analysis of wurtzite (ZnO)1−x(V2O5)x composite

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doi: 10.1088/1674-4926/39/8/082002

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This paper demonstrates the structural, vibrational and photoluminescence characteristics of (ZnO)1−x(V2O5)x (x = 0, 3, 6 and 9 mol%) composites semiconductor synthesized by using the solid state reaction method. X-ray diffraction (XRD) studies show that (ZnO)1−x(V2O5)x composites have the poly crystalline wurtzite structure of hexagonal ZnO. It is found from the XRD results that the lattice constants and the crystallite size increase while the dislocation density decreases with increasing doping concentration. The existence of E1 (TO) and E2 (high) Raman modes show that the ZnO still preserve wurtzite structure after doping vanadium oxide, which is in agreement with XRD results. Room temperature photoluminescence (PL) exhibit near band edge and broad deep level emission while indicating the suppression of deep level emission with the incorporation of V2O5 up to a certain concentration, which is less than 9 mol%. Moreover, the optical band gap increases with doping, which is accompanied by the blue shift of the NBE emission.

• ## Al-free cladding-layer blue laser diodes with a low aspect ratio in far-field beam pattern

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doi: 10.1088/1674-4926/39/8/084004

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c-plane GaN-based blue laser diodes (LDs) were fabricated with Al-free cladding layers (CLs) and deepened etching depth of mesa structure, so the aspect ratio of the far-field pattern (FFP) of the laser beam can be reduced to as low as 1.7, which is nearly the same as conventional AlGaInP-based red LDs. By using GaN CLs, the radiation angle of the laser beam θ is only 10.1° in the direction perpendicular to the junction plane. After forming a deeply etched mesa, the beam divergence angle parallel to the junction plane of FFP, θ//, increases from 4.9° to 5.8°. After using the modified structure, the operation voltage of LD is effectively reduced by 2 V at an injection current of 50 mA, but the threshold current value increases. The etching damage may be one of the main reasons responsible for the increase of the threshold current.

• ## Influence of deposition rate on the structural, optical and electrical properties of electron beam evaporated SnO2 thin films for transparent conducting electrode applications

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doi: 10.1088/1674-4926/39/8/083002

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In this work, the role of deposition rate in the structural, optical and electrical properties of SnO2 thin films deposited by electron beam evaporation method is investigated by varying the deposition powers viz. 50, 75, and 100 W. The structural characterization of the films is done by X-ray diffraction (XRD) technique. The surface morphology of the films is studied by scanning electron microscopy (SEM). Rutherford back scattering (RBS) measurements revealed the thickness of the films ranging from 200 nm to 400 and also a change in the concentration of oxygen vacancies which is found to be the maximum in the film deposited at the lowest deposition rate. Optical absorption spectrum is recorded using the UV–V is spectroscopy and the films are found to be transparent in nature. A shift in the absorption edge is observed and is attributed to a different level of allowed energy states in conduction band minimum. The Hall effect and electrical measurements show a variation in the carrier concentrations, mobility and resistivity of the films. In order to explore a better compromise in electrical and optical properties for transparent electrode applications, skin depths calculations are also done to find the optimized values of carrier concentration and mobility.

• ## Band structure of monolayer of graphene, silicene and silicon-carbide including a lattice of empty or filled holes

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doi: 10.1088/1674-4926/39/8/083001

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We have developed a \begin{document}$\pi$\end{document} -orbital tight-binding Hamiltonian model taking into account the nearest neighbors to study the effect of antidot lattices (two dimensional honeycomb lattice of atoms including holes) on the band structure of silicene and silicon carbide (SiC) sheets. We obtained that the band structure of the silicene antidot superlattice strongly depends on the size of embedded holes, and the band gap of the silicene antidot lattice increases by increasing of holes diameter. The band gap of SiC antidot lattice, except for the lattice of the small unit cell, is independent of the holes diameter and also depends on the distance between holes. We obtained that, the band gap of the SiC antidot lattice is the same as the band gap of the corresponding sheet without hole. Also, the electronic properties of the SiC antidot superlattice occupied either by carbon or by silicon atoms are investigated, numerically. Furthermore, we study the effect of occupation of graphene antidot by Si atoms and vice versa. Also, we have calculated the band structure of graphene and silicene antidot lattice filled by Si + C atoms. Finally, we compute the band structure of the SiC antidot lattice including the holes which are filled by C or by Si atoms. Really, in this paper we have generalized the method of paper[38] about graphene antidot with empty holes to the cases of filled holes by different atoms and also to the case of silicene and silicon carbide antidot lattices.

• ## Design and comparison of new fault-tolerant majority gate based on quantum-dot cellular automata

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doi: 10.1088/1674-4926/39/8/085001

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Quantum-dot cellular automata (QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption. However, in the manufacture of nanoscale devices prone to various forms of defects, which will affect the subsequent circuits design. Therefore, fault-tolerant QCA architectures have become a new research direction. The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells. Compared with the previous structures, the majority gate shows high fault tolerance under single-cell and double-cell omission defects. In order to examine the functionality of the proposed structure, some physical proofs under single cell missing defects are provided. Besides, two new fault-tolerant decoders are constructed based on the proposed majority gate. In order to fully demonstrate the performance of the proposed decoder, the previous decoders were thoroughly compared in terms of fault tolerance, area and delay. The result shows that the proposed design has a good fault tolerance characteristic, while the performance in other aspects is also quite good.

• ## A 0.7–7 GHz wideband reconfigurable receiver RF front-end in CMOS

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doi: 10.1088/1674-4926/39/8/085003

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In this paper, a 0.7–7 GHz wideband RF receiver front-end SOC is designed using the CMOS process. The front-end is composed of two main blocks: a single-ended wideband low noise amplifier (LNA) and an in-phase/quadrature (I/Q) voltage-driven passive mixer with IF amplifiers. Based on a self-biased resistive negative feedback topology, the LNA adopts shunt-peaking inductors and a gate inductor to boost the bandwidth. The passive down-conversion mixer includes two parts: passive switches and IF amplifiers. The measurement results show that the front-end works well at different LO frequencies, and this chip is reconfigurable among 0.7 to 7 GHz by tuning the LO frequency. The measured results under 2.5-GHz LO frequency show that the front-end SoC achieves a maximum conversion gain of 26 dB, a minimum noise figure (NF) of 3.2 dB, with an IF bandwidth of greater than 500 MHz. The chip area is 1.67 × 1.08 mm2.

• ## Research on memory characteristics of microcavity dielectric barrier discharge

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The nonlinear resistance characteristics of microcavity dielectric barrier discharge are mainly studied in the paper. A simulation model of microcavity dielectric barrier discharge is herein built to study the relationship between voltage and current in the process of discharge, and thus its I–V characteristic curve can be obtained. The I–V characteristics of the memristor are analyzed and compared with the I–V characteristics of the dielectric barrier discharge; it can be found that the I–V characteristics of the microcavity dielectric barrier discharge are similar to the characteristics of the memristor by analyzing them. The memory characteristics of microcavity dielectric barrier discharge are further analyzed.