Beta-phase gallium oxide (β-Ga₂O₃) Schottky barrier diodes were fabricated on highly doped single-crystal substrates, where their temperature-dependent electrical properties were comprehensively investigated by forward and reverse current density – voltage and capacitance – voltage characterization. Both the Schottky barrier height and the ideality factor showed a temperature-dependence behavior, revealing the inhomogeneous nature of the Schottky barrier interface caused by the interfacial defects. With a voltage-dependent Schottky barrier incorporated into thermionic emission theory, the inhomogeneous barrier model can be further examined. Furthermore, the reverse leakage current was found to be dominated by the bulk leakage currents due to the good material and surface quality. Leakage current per distance was also obtained. These results can serve as important references for designing efficient β-Ga₂O₃ electronic and optoelectronic devices on highly doped substrates or epitaxial layers.

The 8 μm thick single-crystalline α-Ga₂O₃ epilayers have been heteroepitaxially grown on sapphire (0001) substrates via mist chemical vapor deposition technique. High resolution X-ray diffraction measurements show that the full-widths-at-half-maximum (FWHM) of rocking curves for the (0006) and (10-14) planes are 0.024° and 0.24°, and the corresponding densities of screw and edge dislocations are 9.85 × 10⁷ and 2.85 × 10¹¹ cm⁻², respectively, indicative of high single crystallinity. The out-of-plane and in-plane epitaxial relationships are [0001] α-Ga₂O₃//[0001] α-Al₂O₃ and [11-20] α-Ga₂O₃//[11-20] α-Al₂O₃, respectively. The lateral domain size is in micron scale and the indirect bandgap is determined as 5.03 eV by transmittance spectra. Raman measurement indicates that the lattice-mismatch induced compressive residual strain cannot be ruled out despite the large thickness of the α-Ga₂O₃ epilayer. The achieved high quality α-Ga₂O₃ may provide an alternative material platform for developing high performance power devices and solar-blind photodetectors.

Energy band gap of titanium dioxide (TiO₂) semiconductor plays significant roles in many practical applications of the semiconductor and determines its appropriateness in technological and industrial applications such as UV absorption, pigment, photo-catalysis, pollution control systems and solar cells among others. Substitution of impurities into crystal lattice structure is the most commonly used method of tuning the band gap of TiO₂ for specific application and eventually leads to lattice distortion. This work utilizes the distortion in the lattice structure to estimate the band gap of doped TiO₂, for the first time, through hybridization of a particle swarm optimization algorithm (PSO) with a support vector regression (SVR) algorithm for developing a PSO-SVR model. The precision and accuracy of the developed PSO-SVR model was further justified by applying the model for estimating the effect of cobalt-sulfur co-doping, nickel-iodine co-doping, tungsten and indium doping on the band gap of TiO₂ and excellent agreement with the experimentally reported values was achieved. Practical implementation of the proposed PSO-SVR model would further widen the applications of the semiconductor and reduce the experimental stress involved in band gap determination of TiO₂.

Thermal annealing effects on gamma irradiated Ni/4H-SiC Schottky barrier diode (SBD) characteristics are analyzed over a wide range of temperatures (400–1100 °C). The annealing induced variations in the concentration of deep level traps in the SBDs are identified by thermally stimulated capacitance (TSCAP). A little decrease in the trap density at E_C – 0.63 eV and E_C – 1.13 eV is observed up to the annealing temperature of 600 °C. Whereas, a gamma induced trap at E_C – 0.89 eV disappeared after annealing at 500 °C, revealing that its concentration (< 10¹³ cm⁻³) is reduced below the detection limit of the TSCAP technique. The electrical characteristics of irradiated SBDs are considerably changed at each annealing temperature. To understand the anomalous variations in the post-annealing characteristics, the interface state density distribution in the annealed SBDs is extracted. The electrical properties are improved at 400 °C due to the reduction in the interface trap density. However, from 500 °C, the electrical parameters are found to degrade with the annealing temperature because of the increase in the interface trap density. From the results, it is noted that the rectifying nature of the SBDs vanishes at or above 800 °C.

Monoclinic gallium oxide (Ga₂O₃) has been grown on (0001) sapphire (Al₂O₃) substrate by plasma-assisted molecular beam epitaxy (PA-MBE). The epitaxial relationship has been confirmed to be [010](–201) β-Ga₂O₃||[01–10](0001)Al₂O₃ via in-situ reflection high energy electron diffraction (RHEED) monitoring and ex-situ X-ray diffraction (XRD) measurement. Crystalline quality is improved and surface becomes flatter with increasing growth temperature, with a best full width at half maximum (FWHM) of XRD ω-rocking curve of (–201) plane and root mean square (RMS) roughness of 0.68° and 2.04 nm for the sample grown at 730 °C, respectively. Room temperature cathodoluminescence measurement shows an emission at ~417 nm, which is most likely originated from recombination of donor–acceptor pair (DAP).

The carrier transport mechanism of Mg/Au ohmic contact for lightly doped β-Ga₂O₃ is investigated. An excellent ohmic contact has been achieved when the sample was annealed at 400 °C and the specific contact resistance is 4.3 × 10⁻⁴ Ω·cm². For the annealed sample, the temperature dependence of specific contact resistance is studied in the range from 300 to 375 K. The specific contact resistance is decreased from 4.3 × 10⁻⁴ to 1.59 × 10⁻⁴ Ω·cm² with an increase of test temperature. As combination with the judge of E₀₀, the basic mechanism of current transport is dominant by thermionic emission theory. The effective barrier height between Mg/Au and β-Ga₂O₃ is evaluated to be 0.1 eV for annealed sample by fitting experimental data with thermionic emission model.

We report a high-performance active image sensor pixel design by utilizing amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with a circular structure. The TFT, configured with the inner electrode as source and outer electrode as drain, typically exhibits good saturation electrical characteristics, where the device has a constant drive current despite variations in drain voltage. Due to the very high output resistance exhibited by this asymmetric TFT structure with a circular shape, the pixel circuit considered here in common-drain configuration provides a higher gain of operation than a pixel circuit implemented with rectangular a-IGZO TFTs. They can be used as driving TFTs in active image sensor circuits. They are, therefore, good candidates for digital X-ray detectors in applications such as medical diagnostic procedures.

In this work, the effects of GaN channel traps and temperature on the performance of AlGaN/AlN/GaN/AlGaN high electron mobility transistors (HEMTs) on Si (111) substrate, were investigated. 2D simulations carried out using the Silvaco TCAD simulator tool for different drain and gate voltages showed that acceptor-like traps in the channel have a significant influence on the DC and RF characteristics. It was found that deeper acceptors below the conduction band with larger concentration have a more pronounced effect on the transistor performance. Meanwhile, the donor-like traps show no influence. Pulsing the device with different pulse widths and bias conditions, as well as increasing temperature, showed that the traps are more ionized when the pulse is wider or the temperature is higher, which can degrade the drain current and thus the DC characteristics of the transistor. Passivation of the transistor has also a beneficial effect on performance.

A high-performance single-pole single-throw (SPST) RF switch for mobile phone RF front-end modules (FEMs) was designed and characterized in a 0.13 μm partially depleted silicon-on-insulator (PD SOI) process. In this paper, the traditional series-shunt configuration design was improved by introducing a suitably large DC bias resistor and leakage-preventing PMOS, together with the floating body technique. The performance of the RF switch is greatly improved. Furthermore, a new R_on × C_off testing method is also proposed. The size of this SPST RF switch is 0.2 mm². This switch can be widely used for present 4G and forthcoming 5G mobile phone FEMs.

The three-dimensional hierarchical CuO and Au nanoparticles were synthesized by the hydrothermal method, respectively. The hierarchical CuO and the Au nanoparticles samples were characterized by X-ray diffraction and scanning electronic microscope, respectively. The as-synthesized CuO was assembled regularly from the nanosheets with thickness of 100 nm. The size of Au nanoparticles ranged from 50 to 200 nm. The hierarchical CuO gas sensors modified by different concentration of gold were fabricated. All the Au-loaded CuO gas sensors enhanced the response to ethanol and xylene while reducing the response to methanol, acetone, and formaldehyde. The results indicate that the Au nanoparticles prepared with PVP as surfactant can improve the selectivity of CuO gas sensors to ethanol gas for other common organic volatile gases. The improvement of gas sensing is mainly attributed to the different catalytic efficiency of the Au nanoparticles for different reactions. Meanwhile, the related mechanisms are discussed.

GaN-based continuous-wave operated blue-violet laser diodes (LDs) with long lifetime are demonstrated, which are grown on a c-plane GaN substrate by metal organic chemical vapor deposition with a 10 × 600 μm² ridge waveguide structure. The electrical and optical characteristics of a blue-violet LD are investigated under direct-current injection at room temperature (25 °C). The stimulated emission wavelength and peak optical power of the LD are around 413 nm and over 600 mW, respectively. In addition, the threshold current density and voltage are as small as 1.46 kA/cm² and 4.1 V, respectively. Moreover, the lifetime is longer than 1000 hours under room-temperature continuous-wave operation.

Although tin halide perovskite has shown excellent photoelectric performance, its efficiency of solar cell is low compared with that of lead halide. In order to enhance the efficiency of tin halide perovskite solar cell, a deep understanding of the role of the defects in the perovskite absorption layer and at the electron transport layer (ETL)/absorber or absorber/hole transport layer (HTL) interface is very necessary. In this work, the planar heterojunction-based CH₃NH₃SnI₃ perovskite solar cells were simulated with the SCAPS-1D program. Simulation results revealed a great dependence of device efficiency on defect density and interface quality of the perovskite absorber. The defect density at the front interface is critical for high efficiency, and the polarity of the interface charge has a different impact on the device efficiency. Strikingly, an efficiency over 29% was obtained under the moderate simulation conditions.

Ga₂O₃ metal–oxide–semiconductor field-effect transistors (MOSFETs) with high-breakdown characteristics were fabricated on a homoepitaxial n-typed β-Ga₂O₃ film, which was grown by metal organic chemical vapor deposition (MOCVD) on an Fe-doped semi-insulating (010) Ga₂O₃ substrate. The structure consisted of a 400 nm unintentionally doped (UID) Ga₂O₃ buffer layer and an 80 nm Si-doped channel layer. A high k HfO₂ gate dielectric film formed by atomic layer deposition was employed to reduce the gate leakage. Moreover, a source-connected field plate was introduced to enhance the breakdown characteristics. The drain saturation current density of the fabricated device reached 101 mA/mm at V_gs of 3 V. The off-state current was as low as 7.1 × 10⁻¹¹ A/mm, and the drain current I_ON/I_OFF ratio reached 10⁹. The transistors exhibited three-terminal off-state breakdown voltages of 450 and 550 V, corresponding to gate-to-drain spacing of 4 and 8 μm, respectively.

Reliability issues of flash memory are becoming increasingly significant with the shrinking of technology nodes. Among them, erase time degradation is an issue that draws the attention of academic and industry researchers. In this paper, causes of the " erase time degradation” are exhaustively analyzed, with proposals for its improvement presented, including a low stress program/erase scheme with a staircase pulse and disturb-immune array bias condition. Implementation of the optimized circuit structure is verified in a 128 Mb SPI NOR Flash memory chip, which is fabricated on a SMIC 65 nm ETOX process platform. Testing results indicate a degradation of the sector erase time from 10.67 to 104.9 ms after 10⁵ program/erase cycles, which exhibits an improvement of approximately 100 ms over conventional schemes.