We propose and experimentally demonstrate an integrated silicon photonic scheme to generate multi-channel millimeter-wave (MMW) signals for 5G multi-user applications. The fabricated silicon photonic chip has a footprint of 1.1 × 2.1 mm² and integrates 7 independent channels each having on-chip polarization control and heterodyne mixing functions. 7 channels of 4-Gb/s QPSK baseband signals are delivered via a 2-km multi-core fiber (MCF) and coupled into the chip with a local oscillator (LO) light. The polarization state of each signal light is automatically adjusted and aligned with that of the LO light, and then 7 channels of 28-GHz MMW carrying 4-Gb/s QPSK signals are generated by optical heterodyne beating. Automated polarization-control function of each channel is also demonstrated with ~7-ms tuning time and ~27-dB extinction ratio.

A novel NMOS triggered LIGBT (NTLIGBT) structure is proposed for electrostatic discharge (ESD) protection in this paper. The structure utilizes internal NMOS to trigger SCR-like structure in LIGBT. The trigger voltage is significantly reduced because the embedded NMOS causes N⁺-drain/P-body junction being apt to avalanche breakdown. At the same time, the new parasitic PNP transistor including the newly added P⁺-region as a collector forms another path to bleed ESD current and then the conductivity modulation in the LIGBT is weakened. As a result, the holding voltage is increased. So, the proposed NTLIGBT structure has a narrow ESD design window. The simulation results show an improvement of 71.5% in trigger voltage and over 50% in holding voltage comparing with the conventional LIGBT structure.

In this paper, the impact of extra electron source (EES) and dual metal gate engineering on conventional charge plasma TFET (CP-TFET) have been done for improving DC and Analog/RF parameters. CP-TFET structure is upgraded to double source CP-TFET (DS-CP-TFET) by placing an EES below the source/channel junction for enhancing the device performance in terms of driving current and RF figures of merit (FOMs). But, in spite of these pros, the approach is having cons of higher leakage current similar to MOSFET and negative conductance (inherent nature of TFET). Both the issues have been resolved in the double source dual gate CP-TFET (DS-DG-CP-TFET) by gate workfunction engineering and drain underlapping respectively. Additionally, for getting the optimum performance of DS-DG-CP-TFET, the device sensitivity has been investigated in terms of position of EES, length of drain electrode and workfunction of gate electrode 1 (GE1)

Nanowire (NW) structures is an alternative candidate for constructing the next generation photoelectrochemical water splitting system, due to the outstanding optical and electrical properties. NW photoelectrodes comparing to traditional semiconductor photoelectrodes shows the comparatively shorter transfer distance of photo-induced carriers and the increase amount of the surface reaction sites, which is beneficial for lowering the recombination probability of charge carriers and improving their photoelectrochemical (PEC) performances. Here, we demonstrate for the first time that super-long Cu₂O NWs, more than 4.5 μm, with highly efficient water splitting performance, were synthesized using a cost-effective anodic alumina oxide (AAO) template method. In comparison with the photocathode with planar Cu₂O films, the photocathode with Cu₂O NWs demonstrates a significant enhancement in photocurrent, from –1.00 to –2.75 mA/cm² at –0.8 V versus Ag/AgCl. After optimization of the photoelectrochemical electrode through depositing Pt NPs with atomic layer deposition (ALD) technology on the Cu₂O NWs, the plateau of photocurrent has been enlarged to –7 mA/cm² with the external quantum yield up to 34% at 410 nm. This study suggests that the photoelectrode based on Cu₂O NWs is a hopeful system for establishing high-efficiency water splitting system under visible light.

The inhomogeneous broadening parameter and the internal loss of green LDs are determined by experiments and theoretical fitting. It is found that the inhomogeneous broadening plays an important role on the threshold current density of green LDs. The green LD with large inhomogeneous broadening even cannot lase. Therefore, reducing inhomogeneous broadening is a key issue to improve the performance of green LDs.

As emerging new material, graphene has inspired great research interest. However, most of the studies focused on how to improve the absorption efficiency of graphene, but payed little attention on broadening absorption bandwidth while ensuring high absorption efficiency. In this work, we proposed a hybrid nanostructure, which not only can improve absorption efficiency but also can increase absorption bandwidth. The proposed hybrid nanostructure consists of a monolayer graphene sandwiched between three Ag gratings with different widths and a SiO₂ spacer on a Ag substrate, these three gratings and substrate can excite three independent magnetic dipole resonances. In our calculations, we numerically demonstrate the proposed hybrid structure can achieve graphene absorption bandwidth of 0.311 μm in near-infrared region with absorption exceeding 30% . We also studied absorption peaks dependence on gratings widths and SiO₂ spacer thickness, and explained the results using physical mechanism. Our research can provide a theoretical guidance for future device preparation.

The impact of the V-pits covering layer (VCL) position on the optoelectronic performance of InGaN-based green light-emitting diodes (LEDs) was investigated. It is found that earlier covering of V-pits will hinder the hole injection via the sidewall of V-pits, and then result in less quantum wells (QWs) participating in radioluminescence. The current-voltage characteristics show that the LEDs with earlier covering of V-pits have higher operating voltage at room temperature, and a more dramatic voltage rise with the reduction of temperature. Meanwhile, more manifested emission of sidewall QWs and deeper QWs near to n-type layer was observed at cryogenic temperatures, owing to the earlier V-pits covering leading to more holes being injected via the sidewall of V-pits, which have higher kinetic energy and could transport to deeper QWs.

Based on the silicon-on-insulator (SOI) technology and radiation-hardened silicon gate (RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET (LDMOS) device is presented in this paper. With the gate supply voltage of 30 V, the LDMOS device has a gate oxide thickness of 120 nm, and the RSG process is effective in reducing the total ionizing dose (TID) radiation-induced threshold voltage shift. The p-type ion implantation process and gate-enclosed layout topology are used to prevent radiation-induced leakage current through a parasitic path under the bird's beak and at the deep trench corner, and the device is compatible with high-voltage SOI CMOS process. In the proposed LDMOS, the total ionizing dose radiation degradation for the ON bias is more sensitive than the OFF bias. The experiment results show that the SOI LDMOS has a negative threshold voltage shift of 1.12 V, breakdown voltage of 135 V, and off-state leakage current of 0.92 pA/μm at an accumulated dose level of 100 krad (Si).

Since the proposal of the concept of photonic integrated circuits (PICs), tremendous progress has been made. In 2005, Infinera Corp. rolled out the first commercial PICs, in which hundreds of optical functions were integrated onto a small form factor chip for wavelength division multiplexing (WDM) systems^[1], then a monolithically integrated 10 × 10 Gb/s WDM chip has been demonstrated, the channel number is ten^[2]. Like ICs, large-scale PICs (LS-PICs) will be sure to be pursued. However, there are still some general challenges associated with LS-PICs. The challenges for III–V (mainly InP) PICs is the semiconductor process, which is not mature for LS-PICs. Up to now, the channel number in commercial III–V WDM PICs by Infinera is still about ten or less. For silicon photonics, the challenge is the silicon based light source. The low cost and mature solution for silicon lasers is still unavailable and only 4 × 25 Gb/s PICs are deployed by Intel Corp. after 18-year R&D investment. Thus it is still unavailable for practical LS-PICs in the present times.

Gallium oxide was deposited on a c-plane sapphire substrate by oxygen plasma-assisted pulsed laser deposition (PLD). An oxygen radical was generated by an inductive coupled plasma source and the effect of radio frequency (RF) power on growth rate was investigated. A film grown with plasma assistance showed 2.7 times faster growth rate. X-ray diffraction (XRD) and Raman spectroscopy analysis showed β-Ga₂O₃ films grown with plasma assistance at 500 °C. The roughness of the films decreased when the RF power of plasma treatment increased. Transmittance of these films was at least 80% and showed sharp absorption edge at 250 nm which was consistent with data previously reported.

Reliability issues of flash memory are becoming increasingly significant with the shrinking of technology nodes. Among them, erase time degradation is an issue that draws the attention of academic and industry researchers. In this paper, causes of the " erase time degradation” are exhaustively analyzed, with proposals for its improvement presented, including a low stress program/erase scheme with a staircase pulse and disturb-immune array bias condition. Implementation of the optimized circuit structure is verified in a 128 Mb SPI NOR Flash memory chip, which is fabricated on a SMIC 65 nm ETOX process platform. Testing results indicate a degradation of the sector erase time from 10.67 to 104.9 ms after 10⁵ program/erase cycles, which exhibits an improvement of approximately 100 ms over conventional schemes.