Recently, C₅₆₈ has emerged as a new carbon allotrope, which shows semiconducting properties with a band gap around 1 eV and has attracted much attention. In this work, the external strain effects on the electronic properties of C₅₆₈ have been studied theoretically through first-principle calculations. The numerical results show that while in-plane uniaxial and biaxial strains both reduces the band gap of C₅₆₈ in case of tensile strain, their effects are quite different in case of compressive strain. With increasing compressive uniaxial strain, the band gap of C₅₆₈ first increases, and then dramatically decreases. In contrast, the application of compressive biaxial strain up to –10% only leads to a slight increase of band gap. Moreover, an indirect-to-direct gap transition can be realized under both types of compressive strain. The results also show that the optical anisotropy of C₅₆₈ can be induced under uniaxial strain, while biaxial strain does not cause such an effect. These results indicate good strain tunability of the band structure of C₅₆₈, which could be helpful for the design and optimization of C₅₆₈-based nanodevices.

In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.

A single-pole four-throw (SP4T) RF switch with charge-pump-based controller is designed and implemented in a commercial 130-nm silicon-on-insulator (SOI) CMOS process. An improved body self-biasing technique based on diodes is utilized to simplify the controlling circuitry and improve the linearity. A multistack field-effect-transistor (FET) structure with body floating technique is employed to provide good power-handling capability. The proposed design demonstrates a measured input 0.1-dB compression point of 38.5 dBm at 1.9 GHz, an insertion loss of 0.27 dB/0.33 dB and an isolation of 35 dB/27 dB at 900 MHz/1.9 GHz, respectively. The overall chip area is only 0.49 mm². This RF switch can be used in GSM/WCDMA/LTE front-end modules.

Black phosphorous (BP), an excellent two-dimensional (2D) monoelemental layered p-type semiconductor material with high carrier mobility and thickness-dependent tunable direct bandgap structure, has been widely applied in various devices. As the essential building blocks for modern electronic and optoelectronic devices, high quality PN junctions based on semiconductors have attracted widespread attention. Herein, we report a junction field-effect transistor (JFET) by integrating narrow-gap p-type BP and ultra-wide gap n-type β-Ga₂O₃ nanoflakes for the first time. BP and β-Ga₂O₃ form a vertical van der Waals (vdW) heterostructure by mechanically exfoliated method. The BP/β-Ga₂O₃ vdW heterostructure exhibits remarkable PN diode rectifying characteristics with a high rectifying ratio about 10⁷ and a low reverse current around pA. More interestingly, by using the BP as the gate and β-Ga₂O₃ as the channel, the BP/β-Ga₂O₃ JFET devices demonstrate excellent n-channel JFET characteristics with the on/off ratio as high as 10⁷, gate leakage current around as low as pA, g_m up to 25.3 µS and I_DSS of 16.5 µA/µm. Moreover, it has a pinch-off voltage of –20 V and a minimum subthreshold swing of 260 mV/dec. These excellent n-channel JFET characteristics will expand the application of BP in future nanoelectronic devices.

Two-dimensional material has been regarded as a competitive silicon-alternative with gate length approaching sub-10 nm, due to its unique atomic thickness and outstanding electronic properties. Herein, we provide a comprehensively study on the electronic and ballistic transport properties of the puckered arsenene by the density functional theory coupled with nonequilibrium Green’s function formalism. The puckered arsenene exhibits an anisotropic characteristic, as effective mass for electron/hole in the armchair and zigzag directions is 0.35/1.26 m₀ and 0.16/0.32 m₀. And it also holds a high electron mobility, as the highest value can reach 20 045 cm²V^–1s^–1. Moreover, the puckered arsenene FETs with 10-nm channel length possess high on/off ratio above 10⁵ and steep subthreshold swing below 75 mV/dec, which have the potential to design high-performance electronic devices. Interestingly, the channel length limit for arsenene FETs can reach 7-nm. Furthermore, the benchmarking of the intrinsic arsenene FETs and the 32-bit arithmetic logic unit circuits also shows that such devices possess high switching speed and low energy dissipation, which can be comparable to the CMOS technologies and other CMOS alternatives. Therefore, the puckered arsenene is an attractive channel material in the next-generation electronics.

Precise spatial control of 2D materials is the key capability of engineering their optical, electronic, and mechanical properties. However, growth of novel 2D Mo₂C on Cu surface by chemical vapor deposition method was revealed to be seed-induced 2D growth, limiting further synthesis of complex Mo₂C spatial structures. In this research, we demonstrate the controlled growth of Mo₂C pyramids with numerous morphologies, which are characterized with clear terraces within the structures. The whole evolution for Mo₂C pyramids in the coursed of CVD process has been detected, posing significant potential in probing growth mechanism. The formation of the Mo₂C pyramids arises from the supersaturation-induced nucleation and concentration-gradient driven diffused growth of a new Mo₂C layer on the edged areas of intrinsic ones, as supported by STEM imaging. This work provides a novel Mo₂C-based pyramid structure and further reveals a sliding growth mechanism, which could offer impetus for the design of new 3D spatial structures of Mo₂C and other 2D materials.

In this paper, drain current transient characteristics of β-Ga₂O₃ high electron mobility transistor (HEMT) are studied to access current collapse and recovery time due to dynamic population and de-population of deep level traps and interface traps. An approximately 10 min, and 1 h of recovery time to steady-state drain current value is measured under 1 ms of stress on the gate and drain electrodes due to iron (Fe)–doped β-Ga₂O₃ substrate and germanium (Ge)–doped β-Ga₂O₃ epitaxial layer respectively. On-state current lag is more severe due to widely reported defect trap E_C – 0.82 eV over E_C – 0.78 eV, −0.75 eV present in Iron (Fe)-doped β-Ga₂O₃ bulk crystals. A negligible amount of current degradation is observed in the latter case due to the trap level at E_C – 0.98 eV. It is found that occupancy of ionized trap density varied mostly under the gate and gate-source area. This investigation of reversible current collapse phenomenon and assessment of recovery time in β-Ga₂O₃ HEMT is carried out through 2D device simulations using appropriate velocity and charge transport models. This work can further help in the proper characterization of β-Ga₂O₃ devices to understand temporary and permanent device degradation.

A novel 600 V snapback-free high-speed silicon-on-insulator lateral insulated gate bipolar transistor is proposed and investigated by simulation. The proposed device features an embedded NPN structure at the anode side, and double trenches together with an N-type carrier storage (N-CS) layer at the cathode side, named DT-NPN LIGBT. The NPN structure not only acts as an electron barrier to eliminate the snapback effect in the on-state within a smaller cell pitch but also provides an extra electron extracting path during the turn-off stage to decrease the turnoff loss (E_off). The double cathode trenches and N-CS layer hinder the hole from being extracted by the cathode quickly. They then enhance carrier storing effect and lead to a reduced on-state voltage drop (V_on). The latch-up immunity is improved by the double cathode trenches. Hence, the DT-NPN LIGBT obtains a superior tradeoff between the V_on and E_off. Additionally, the DT-NPN LIGBT exhibits an improved blocking capability and weak dependence of breakdown voltage (BV) on the P⁺ anode doping concentration because the NPN structure suppresses triggering the PNP transistor. The proposed LIGBT reduces the E_off by 55% at the same V_on, and improves the BV by 7.3% compared to the conventional LIGBT.

Traditional magnetically coupled resonant wireless power transfer technology uses fixed distances between coils for research, to prevent fluctuations in the receiving voltage, and lead to reduce transmission efficiency. This paper proposes a closed-loop control wireless communication wireless power transfer system with a wearable four-coil structure to stabilize the receiving voltage fluctuation caused by changes in the displacement between the coils. Test results show that the system can provide stable receiving voltage, no matter how the distance between the transmitting coil and the receiving coil is changed. When the transmission distance is 20 mm, the power transfer efficiency of the system can reach 18.5% under the open-loop state, and the stimulation parameters such as the stimulation period and pulse width can be adjusted in real time through the personal computer terminal.

This study proposes a new generation of floating gate transistors (FGT) with a novel built-in security feature. The new device has applications in guarding the IC chips against the current reverse engineering techniques, including scanning capacitance microscopy (SCM). The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate, even in nano-meter scales. The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate. This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic. Furthermore, this model was verified with a simulation. In addition, the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor. The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated. Finally, the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.

When preparing large monocrystalline silicon materials, severe carbon etching and silicide deposition often occur to the thermal system. Therefore, a suppression method that optimizes the upper insulation structure has been proposed. Assisted by the finite element method, we calculated temperature distribution and carbon deposition of heater and heat shield, made the rule of silicide and temperature distributing in the system, and we explained the formation of impurity deposition. Our results show that the optimized thermal system reduces carbon etching loss on heat components. The lowered pressure of the furnace brings a rapid decrease of silicide deposition. The increase of the argon flow rate effectively inhibits CO and back diffusion. The simulated results agree well with the experiment observations, validating the effectiveness of the proposed method.

Global data traffic is growing rapidly, and the demand for optoelectronic transceivers applied in data centers (DCs) is also increasing correspondingly. In this review, we first briefly introduce the development of optoelectronics transceivers in DCs, as well as the advantages of silicon photonic chips fabricated by complementary metal oxide semiconductor process. We also summarize the research on the main components in silicon photonic transceivers. In particular, quantum dot lasers have shown great potential as light sources for silicon photonic integration—whether to adopt bonding method or monolithic integration—thanks to their unique advantages over the conventional quantum-well counterparts. Some of the solutions for high-speed optical interconnection in DCs are then discussed. Among them, wavelength division multiplexing and four-level pulse-amplitude modulation have been widely studied and applied. At present, the application of coherent optical communication technology has moved from the backbone network, to the metro network, and then to DCs.

Au80Sn20 alloy is a widely used solder for laser diode packaging. In this paper, the thermal resistance of GaN-based blue laser diodes packaged in TO56 cans were measured by the forward voltage method. The microstructures of Au80Sn20 solder were then investigated to understand the reason for the difference in thermal resistance. It was found that the microstructure with a higher content of Au-rich phase in the center of the solder and a lower content of (Au,Ni)Sn phase at the interface of the solder/heat sink resulted in lower thermal resistance. This is attributed to the lower thermal resistance of Au-rich phase and higher thermal resistance of (Au,Ni)Sn phase.

In this work, forward current voltage characteristics for multi-quantum wells Al_0.33Ga_0.67As Schottky diode were measured at temperature ranges from 100 to 300 K. The main parameters of this Schottky diode, such as the ideality factor, barrier height, series resistance and saturation current, have been extracted using both analytical and heuristics methods. differential evolution (DE), particle swarm optimization (PSO) and artificial bee colony (ABC) have been chosen as candidate heuristics algorithms, while Cheung technic was selected as analytical extraction method. The obtained results show clearly the high performance of DE algorithms in terms of parameters accuracy, convergence speed and robustness.

This paper reports the realization of planar Schottky diodes based on nanorod ZnO thin film. The nanorod ZnO thin film was fabricated by hydrothermal technique on boron doped p-type Si (100) substrate. The Ag//ZnO/Al planar diode operating with voltage bias from –3 to 3 V. The I–V characteristics clearly indicate that the devices have rectifying performance. The thermionic emission theory governs the current across the studied Schottky diode. The device achieved a turn-on voltage of 0.9 V, barrier height 0.69 eV and saturation current of 1.2 × 10^–6 A. The diode shows a very large ideality factor (n > > 2) which is attributed to high interface trap concentration. The surface topology was investigated by scanning electron microscope (SEM). The structural properties of the nanostructured ZnO thin film were characterized by X-ray diffraction (XRD). The SEM images reveal that the ZnO nanorods grow perpendicular to the substrate with uniformity and high density. The XRD pattern illustrates the dominant peak appearing at (002). This intense peak indicates the c-axis orientated phase of the wurtzite ZnO structure. It demonstrates that the crystals grow uniformly perpendicular to the substrate surface in good agreement with the SEM images.

To improve the full-well capacity and linear dynamic range of CMOS image sensor, a special finger-shaped pinned photodiode (PPD) is designed. In terms of process, the first N-type ion implantation of the PPD N buried layer is extended under the transfer gate, thereby increasing the PPD capacitance. Based on TCAD simulation, the width and spacing of PPD were precisely adjusted. A high full-well capacity pixel design with a pixel size of 6 × 6 μm² is realized based on the 0.18 μm CMOS process. The simulation results indicate that the pixel with the above structure and process has a depletion depth of 2.8 μm and a charge transfer efficiency of 100%. The measurement results of the test chip show that the full-well capacity can reach 68650e^–. Compared with the conventional structure, the proposed PPD structure can effectively improve the full well capacity of the pixel.

The purpose of this work is to analyze the electrical properties of the metal–semiconductor contact (MSC) in the framework of the theory of complex systems. The effect of inhomogeneity of the different microstructures: polycrystalline, monocrystalline, amorphous metal–semiconductor contact surface is investigated, considering a Schottky diode (SD) as a parallel connection of numerous subdiodes. It has been shown that the polycrystallinity of the metal translates a homogeneous contact into a complex system, which consists of parallel connected numerous elementary contacts having different properties and parameters.

A novel 4H-SiC trench MOSFET is presented and investigated by simulation in this paper. The device features an integrated Schottky barrier diode and an L-shaped P⁺ shielding region beneath the gate trench and aside one wall of the gate trench (S-TMOS). The integrated Schottky barrier diode works as a free-wheeling diode in reverse recovery and reverse conduction, which significantly reduces reverse recovery charge (Q_rr) and reverse turn-on voltage (V_F). The L-shaped P⁺ region effectively shields the coupling of gate and drain, resulting in a lower gate–drain capacitance (C_gd) and date–drain charge (Q_gd). Compared with that of conventional SiC trench MOSFET (C-TMOS), the V_F and Q_rr of S-TMOS has reduced by 44% and 75%, respectively, with almost the same forward output current and reverse breakdown voltage. Moreover, the S-TMOS reduces Q_gd and C_gd by 32% and 22%, respectively, in comparison with C-TMOS.

The defect properties in d-electron containing materials will be strongly influenced by the non-negligible on-site Coulomb interactions. However, this has been omitted in the current widely adopted standard first-principles calculations, such as LDA, leading to a large deviation of calculated results. Therefore, as a comparative case study, in this paper the defects of CdTe are investigated by first-principles calculations including standard LDA and LDA + U, and we find that LDA + U gives more accurate formation energies of the neutral point defects than the standard LDA. The same trend can be found in transition energies of the charged state defects as well. These comparative analyses show that LDA + U gives better results for the defects of CdTe than the standard LDA and requires less computing resource than LAPW, indicating it should have huge potential to model supercells with large number of atoms and strong electron interactions. Moreover, a new anion interstitial defect structure is found to be more stable than the well-known tetrahedron central anion interstitial defect structure \begin{document}${\rm{Te}}_i^a$\end{document}.

Based on the density functional theory, the energy band and electronic structure of β-CuGaO₂ are calculated by the modified Becke-Johnson plus an on-site Coulomb U (MBJ + U) approach in this paper. The calculated results show that the band gap value of β-CuGaO₂ obtained by the MBJ + U approach is close to the experimental value. The calculated results of electronic structure indicate that the main properties of the material are determined by the bond between Cu-3d and O-2p energy levels near the valence band of β-CuGaO₂, while a weak anti-bond combination is formed mainly by the O-2p energy level and Ga-4s energy level near the bottom of the conduction band of β-CuGaO₂. The β-CuGaO₂ thin film is predicted to hold excellent photovoltaic performance by analysis of the spectroscopic limited maximum efficiency (SLME) method. At the same time, the calculated maximum photoelectric conversion efficiency of the ideal CuGaO₂ solar cell is 32.4%. Relevant conclusions can expand β-CuGaO₂ photovoltaic applications.