A C-band polarization rotator-splitter based on a mode-evolution structure and an asymmetric directional coupler is proposed. The mode-evolution structure is designed in a bi-level taper through which the TM₀ mode can evolve into the TE₁ mode. Then the TE₁ mode is coupled to the TE₀ mode at the cross port using the asymmetric directional coupler. The input TE₀ mode propagates along the waveguide without mode conversion and output at the through port. From the experimental results, the extinction ratio is lower than 30 dB and the excess loss is less than 1 dB for input TE₀ mode at the whole C-band. For input TM₀ mode, the ER and the EL are, respectively, lower than −10 and 1.5 dB.

This paper proposes a fast-locking bang-bang phase-locked loop (BBPLL). A novel adaptive loop gain controller (ALGC) is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector (BBPFD) with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm². Measured results show that the BBPLL operates at a frequency range from 0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1 μs @ 100 MHz frequency jump. The figure-of-merit of the fast-locking BBPLL is −334 dB.

In this paper a 0.6 V, 14 bit/500 Hz subthreshold inverter-based sigma–delta modulator is proposed. In the first integrator of the modulator, a bootstrap switch is used to accomplish accurate signal sampling. Without a transconductor operational amplifier (OTA), the sigma–delta modulator adopts a cascode inverter in the subthreshold region to save power consumption. The modulator is fabricated with a 0.13 μm CMOS mixed-signal process. The experiment results show that with the 0.6 V power supply it achieves a maximum SNDR of 69.7 dB and an ENOB of 11.3 bit, respectively, but only consumes 5.07 μw power dissipation.

Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs (short channel effects) in sub 22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2 (conventional HfO₂ spacer SOI FinFET) and device-D3 (source/drain extended HfO₂ spacer SOI FinFET) over the device-D1 (conventional Si₃N₄ spacer SOI FinFET) at 20 nm technology node through the 3-D (dimensional) simulation process. The major performance parameters like I_on (ON current), I_off (OFF current), g_m (transconductance), g_d (output conductance), A_V (intrinsic gain), SS (sub-threshold slope), TGF = g_m/I_d (trans-conductance generation factor), V_EA (early voltage), GTFP (gain trans-conductance frequency product), TFP (tans-conductance frequency product), GFP (gain frequency product), and f_T (cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation, device-D3 and D2 give better results in terms of g_m, I_D (drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f_T, GTFP, TFP, and GFP parameters both at low and high values of V_DS = 0.05 V and V_DS = 0.7 V respectively.

Mode-division multiplexing (MDM) has become an increasingly important technology to further increase the transmission capacity of both optical-fiber-based communication networks, data centers and waveguide-based on-chip optical interconnects. Mode manipulation devices are indispensable in MDM system and have been widely studied in fiber, planar lightwave circuits, and silicon and InP based platforms. InP-based integration technology provides the easiest accessibility to bring together the functions of laser sources, modulators, and mode manipulation devices into a single chip, making it a promising solution for fully integrated few-mode transmitters in the MDM system. This paper reviews the recent progress in InP-based mode manipulation devices, including the few-mode converters, multiplexers, demultiplexers, and transmitters. The working principle, structures, and performance of InP-based few-mode devices are discussed.

This paper presents a new model to study the static performances of a GaN metal epitaxial-semiconductor field effect transistor (MESFET) based on the metal-semiconductor interface state of the Schottky junction. The I–V performances of MESFET under different channel lengths and different operating systems (pinch-off or not) have been achieved by our model, which strictly depended on the electrical parameters, such as the drain-gate capacity C_gd, the source-gate capacity C_gs, the transconductance, and the conductance. To determine the accuracy of our model, root-mean-square (RMS) errors were calculated. In the experiment, the experimental data agree with our model. Also, the minimum value of the electrical parameter has been calculated to get the maximum cut-off frequency for the GaN MESFET.

A novel power-on-reset (POR) circuit with simple architecture, small values of capacitances, ultra-lower power consumption, and self-adjustable delay time of reset pulse for passive UHF RFID tags is presented in this paper. A proposed delay element was adopted for the features of small capacitances and wide power supply rise time range. An inverter was used as a two-inputs logic device to simplify the architecture of the circuit. The technology used for design and simulation is SMIC 0.18 μm RF. Simulation results show that the circuit functions well under different process corners with different power supply rise time, and is able to generate a POR signal after the power supply is briefly powered off. The static power consumption is less than 30 pA. Moreover, the circuit operates properly along with other modules of analog front-end.

In the process of producing a white light emitting diode, the consistency of the optical coherence and stability of the photochromic properties is a crucial index for measuring the quality of the product. Phosphor sedimentation is a significant factor affecting optical coherence, thus, in this paper, seven sets of control experiments were set up with the phenomenon of the phosphor precipitation at time intervals 0, 2, 5, 10, 20, 30, and 40 min. The color coordination concentration and optical properties were also tested. The results indicate that phosphor sedimentation occurs between 0 and 20 min, during which the color coordinate placement is concentrated, the central coordinates are (x = 0.4432 ± 0.004, y = 0.4052 ± 0.002); the quality was verified because the Supply Demand Chain Management (SDCM) was no greater than 7. Later, between 30 and 40 min, the central coordinates are (x = 0.4366 ± 0.003, y = 0.4012 ± 0.003), which had an SDCM value higher than 7, and had a more discrete color placement; it does not meet the requirements of the national standard GBT24823-2016 general lighting LED module performance.

Zinc sulphide (ZnS) thin films have grown on glass and Si substrates by reactive cathodic radio frequency (RF) sputtering. The RF power was varied in the range of 100 to 250 W, while the deposition time is set at 75 min. The optical, structural, and morphological properties of these thin films have been studied. The optical properties (mainly thickness, refractive index, absorption coefficient, and optical band gap) were investigated by optical transmittance measurements in the wavelength range of ultraviolet-visible-near infrared spectroscopy and spectroscopy infrared with Fourier transform. Fourier (FT-IR). XRD analysis indicated that all sputtering ZnS films had a single-phase with a preferred orientation along the (111) plane of the zinc sphalerite phase (ZB). The crystallite size ranged from 11.5 to 48.5 nm with RF power getting a maximum of 200 W. UV–visible measurements exhibited that the ZnS film had more than 80% transmission in the visible wavelength region. In addition, it has been observed that the band gap energy of ZnS films is decreased slightly from 3.52 to 3.29 eV, and as the RF power is increased, the film thickness increases with the speed of deposit growth. Scanning electron microscopy observations revealed the types of smooth-surfaced films. The measurements (FT-IR) revealed at wave number 1118 and 465.02 cm⁻¹ absorption bands corresponding to the symmetrical and asymmetric vibration of the Zn-S stretching mode. X-ray reflectometry measurements of ZnS films have shown that the density of the films is (3.9 g/cm³) close to that of solid ZnS.

Over the past few years, Cu-based materials have been intensively studied focusing on their structural and thermoelectric properties. In this work, copper sulphide powders were synthesized by the sol-gel method. The chemical composition and the morphological properties of the obtained samples were analyzed by X-ray diffraction, differential thermal analysis, and scanning electron microscopy. It is shown that the decomposition from one phase to another can be obtained by annealing. The electrical resistivity and the crystallite size were found to be strongly affected by the phase transition. Thermoelectric analyses showed that the digenite phase exhibits the highest power factor at room temperature. The Seebeck coefficient of the compound Cu_1.8S shows a pronounced peak at the γ–β transition temperature. This behavior was statistically explained in terms of a dramatic increase in the disorder in the atoms-carriers ensemble.

A 2nd transconductance subharmonic receiver for 245 GHz spectroscopy sensor applications has been proposed. The receiver consists of a 245 GHz on-chip folded dipole antenna, a CB (common base) LNA, a 2nd transconductance SHM (subharmonic mixer), and a 120 GHz push-push VCO with 1/64 divider. The receiver is fabricated in f_T/f_max = 300/500 GHz SiGe:C BiCMOS technology. The receiver dissipates a low power of 288 mW. Integrated with the on-chip antenna, the receiver is measured on-chip with a conversion gain of 15 dB, a bandwidth of 15 GHz, and the chip will be utilized in PCB board design for gas spectroscopy sensor application.

The leakage current and breakdown voltage of AlGaN/GaN/AlGaN high electron mobility transistors on silicon with different GaN channel thicknesses were investigated. The results showed that a thin GaN channel was beneficial for obtaining a high breakdown voltage, based on the leakage current path and the acceptor traps in the AlGaN back-barrier. The breakdown voltage of the device with an 800 nm-thick GaN channel was 926 V @ 1 mA/mm, and the leakage current increased slowly between 300 and 800 V. Besides, the raising conduction band edge of the GaN channel by the AlGaN back-barrier lead to little degradation for sheet 2-D electron gas density, especially, in the thin GaN channel. The transfer and output characteristics were not obviously deteriorated for the samples with different GaN channel thickness. Through optimizing the GaN channel thickness and designing the AlGaN back-barrier, the lower leakage current and higher breakdown voltage would be possible.

The investigation of the interband type-II superlattice InAs/GaSb cascade photodetector in the temperature range of 320–380 K is presented in this paper. The article is devoted to the theoretical modeling of the cascade detector characteristics by the use of the SimuApsys platform and the 4-band model (k∙p 8 × 8 method). The obtained theoretical characteristics are comparable with experimentally measured ones, suggesting that transport in the absorber is determined by the dynamics of intrinsic carriers and by their lifetime. An overlap equal to 120 meV was used in calculations and a correction term in the " non-common atom” model H_xy = 700 meV was added to the Hamiltonian. The electron and hole effective masses from dispersion curves were estimated and absorption coefficient α was calculated. Based on the simulation detectivity, D^* characteristics in the temperature range 320–380 K were calculated. The simulated theoretical characteristics at 320 K are comparable to experimentally measured ones, however at higher temperatures, the experimental value of D^* does not reach the theoretical values due to the low resistance of the device and short diffusion length.

We use an electro-thermal coupled Monte Carlo simulation framework to investigate the self-heating effect (SHE) in 14 nm bulk nFinFETs with ambient temperature (T_A) from 220 to 400 K. Based on this method, non-local heat generation can be achieved. Contact thermal resistances of Si/Metal and Si/SiO₂ are selected to ensure that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) not all input power (Q_input) turns into heat generation in the device region and some is taken out by the thermal non-equilibrium carriers, owing to the serious non-equilibrium transport; (ii) a higher T_A leads to a larger ratio of input power turning into heat generation in the device region at the same operating voltages; (iii) SHE can lead to serious degradation in the carrier transport, which will increase when T_A increases; (iv) the current degradation can be 8.9% when V_ds = 0.7 V, V_gs = 1 V and T_A = 400 K; (v) device thermal resistance (R_th) increases with increasing of T_A, which is seriously impacted by the non-equilibrium transport. Hence, the impact of T_A should be carefully considered when investigating SHE in nanoscale devices.

A high-order curvature-compensated CMOS bandgap reference (BGR) topology with a low temperature coefficient (TC) over a wide temperature range and a high power supply reject ratio (PSRR) is presented in this paper. High-order correction is realized by incorporating a nonlinear current I_NL, which is generated by ∆V_GS across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of 0.19 ppm/°C over the temperature range of 165 °C (−40 to 125 °C), PSRR of −123 dB @ DC and −56 dB @ 100 kHz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.

Physics equation-based semiconductor device modeling is accurate but time and money consuming. The need for studying new material and devices is increasing so that there has to be an efficient and accurate device modeling method. In this paper, two methods based on multivariate rational regression (MRR) for device modeling are proposed. They are single-pole MRR and double-pole MRR. The two MRR methods are proved to be powerful in nonlinear curve fitting and have good numerical stability. Two methods are compared with OLS and LASSO by fitting the SMIC 40 nm MOS-FET I–V characteristic curve and the normalized mean square error of Single-pole MRR is \begin{document}$3.02 \times {10^{{\rm{ - }}8}}$\end{document} which is 4 magnitudes less than an ordinary least square. The I–V characteristics of CNT-FET and performance indicators (noise factor, gain, power) of a low noise amplifier are also modeled by using MRR methods. The results show MRR methods are very powerful methods for semiconductor device modeling and have a strong nonlinear curve fitting ability.

An SOI trench LDMOST (TLDMOST) with ultra-low specific on-resistance (R_on,sp) is proposed. It features double vertical high-k insulator pillars (Hk₁ and Hk₂) in the oxide trench, which are connected to the source electrode and drain electrode, respectively. Firstly, under reverse bias voltage, most electric displacement lines produced by the charges of the depleted drift region in the source side go through the Hk₁, and thus the average electric field strength under the source can be enhanced. Secondly, two additional electric field peaks are induced by the Hk₁, which further modulate the electric field in the drift region under the source. Thirdly, most electric displacement lines produced by the charges of the depleted drift region in the drain side enter into the Hk₂. This not only introduces one more electric field peak at the corner of the oxide trench around the Hk₂, but also forms the enhanced vertical reduced surface field effect, which modulates the electric field in the drift region under the drain. With the effects of the two Hk insulator pillars, the breakdown voltage (BV) and the drift region doping concentration are significantly improved. The simulation results indicate that compared with the oxide trench LDMOST (previous TLDMOST) with the same geometry, the proposed double Hk TLDMOST enhances the BV by 86% and reduces the R_on,sp by 88%.

This article presents a low voltage low power configuration of current differencing transconductance amplifier (CDTA) based on floating gate MOSFET. The proposed CDTA variant operates at lower supply voltage ±1.4 V with total static power dissipation of 2.60 mW due to the low voltage feature of floating gate MOSFET. High transconductance up to 6.21 mA/V is achieved with extended linear range of the circuit i.e. ±130 μA. Two applications are illustrated to demonstrate the effectiveness of the proposed active block. A quadrature oscillator is realized using FGMOS based CDTA, two capacitors, and a resistor. The resistor is implemented using two NMOSFETs to provide high linearity and tunablility. Another application is the Schmitt trigger circuit based on the proposed CDTA variant. All circuits are simulated by using SPICE and TSMC 130 nm technology.

In order to reduce the temperature measurement error with the uncooled infrared thermal imager, experiments were conducted to evaluate the effects of environment temperature and measurement distance on the measurement error of human eye temperature. First, the forehead temperature was used as an intermediate variable to obtain the actual temperature of human eyes. Then, the effects of environment temperature and measurement distance on the temperature measurement were separately analyzed. Finally, an empirical model was established to correlate actual eye temperature with the measured temperature, environment temperature, and measurement distance. To verify the formula, three different environment temperatures were tested at different distances. The measurement errors were substantially reduced using the empirical model for temperature correction. The results show that this method can effectively improve the accuracy of temperature measurement using the infrared thermal imager.

ZnO nanowires (NWs) layers have been synthesized using a two-step chemical solution method on ITO glass substrates coated with ZnO seeds at different immersing times. The structures, morphology and optical properties of the synthesized ZnO NWs have been investigated. The prepared ZnO NWs have an obvious polycrystalline hexangular wurtzite structure and are preferentially oriented along the c-axis (002). FESEM micrographs showed that the prepared ZnO NWs are close to being vertically grown and more densely at higher immersing times. Poly [2-methoxy-5(2′-ethyl-hexyloxy)-1,4-phenylenevinylene], MEH-PPV, was used as an active layer to prepare three samples of MEH-PPV/ZnO solar cell based on ZnO NWs that were prepared at different immersing times. A maximum power conversion efficiency of 0.812% was achieved for MEH-PPV/ZnO solar cell prepared at a higher immersing time. The improved efficiency may be attributed to the enhancement of both open-circuit voltage and fill factor.

Trap-induced current collapse has become one of the critical issues hindering the improvement of GaN-based microwave power devices. It is difficult to study the behavior of each trapping effect separately with the experimental measurement. Transient simulation is a useful technique for analyzing the mechanism of current collapse. In this paper, the coeffect of surface- and bulk-trapping behaviors on the performance of AlGaN/GaN HEMTs is investigated based on the two-dimensional (2D) transient simulation. In addition, the mechanism of trapping effects is analyzed from the aspect of device physics. Two simulation models with different types of traps are used for comparison, and the simulated results reproduced the experimental measured data. It is found that the final steady-state current decreases when both the surface and bulk traps are taken into account in the model. However, contrary to the expectation, the total current collapse is dramatically reduced (e.g. from 18% to 4% for the 90 nm gate-length device). The results suggest that the surface-related current collapse of GaN-based HEMTs may be mitigated in some degree due to the participation of bulk traps with short time constant. The work in this paper will be helpful for further optimization design of material and device structures.

The aim of this work is to investigate the dependence of ZnS thin films structural and optical properties with the solution flow rate during the deposition using an ultrasonic spray method. The solution flow rate ranged from 10 to 50 mL/h and the substrate temperature was maintained at 450 °C. The effect of the solution flow rate on the properties of ZnS thin films was investigated by X-ray diffraction (XRD), scanning electron microscopy (SEM), optical transmittance spectroscopy (UV–V) and the four-point method. The X-ray diffraction analysis showed that the deposited material was pure zinc sulphide, it has a cubic sphalerite structure with preferential orientation along the (111) direction. The grain size values were calculated and found to be between 38 to 82 nm. SEM analysis revealed that the deposited thin films have good adherence to the substrate surfaces, are homogeneous and have high density. The average transmission of all films is up more than 65% in the range wavelength from 200 to 1100 nm and their band gap energy values were found between 3.5–3.92 eV. The obtained film thickness varies from 390 to 1040 nm. Moreover, the electric resistivity of the deposited films increases with the increasing of the solution flow rate between 3.51 × 10⁵ and 11 × 10⁵ Ω·cm.

Six-junction vertically-stacked GaAs laser power converters (LPCs) with n⁺-GaAs/p⁺-Al_0.37Ga_0.63As tunnel junctions have been designed and grown by metal-organic chemical vapor deposition for converting the power of 808 nm lasers. The LPC chips are characterized by measuring current–voltage (I–V) characteristics under 808 nm laser illumination, and a maximum conversion efficiency η_c of 53.1% is obtained for LPCs with an aperture diameter of 2 mm at an input laser power of 0.5 W. In addition, the characteristics of the LPCs are analyzed by a standard equivalent-circuit model, and the reverse saturation current, ideality factor, series resistance and shunt resistance are extracted by fitting of the I–V curves.

In this paper, theoretical research on the heat accumulation effect of a Darlington transistor induced by high power microwave is conducted, and temperature variation as functions of pulse repetitive frequency (PRF) and duty cycle (DC) are studied. According to the distribution of the electronic field and the current density in the Darlington transistor, the research of the damage mechanism is carried out. The results show that for repetitive pulses with the same pulse widths and different PRFs, the value of temperature variation increases with PRF increases, and the peak temperature has almost no change when PRF is lower than 200 kHz; while for the repetitive pulses with the same PRF and different pulse widths, the larger the pulse width is, the greater temperature variation varies. The response of the peak temperature caused by a single pulse demonstrates that there is no temperature variation when the rising time is much shorter than the falling time. In addition, the relationship between the temperature variation and the time during the rising edge time as well as that between the temperature variation and the time during the falling edge time are obtained utilizing the curve fitting method. Finally, for a certain average power, with DC increases the value of temperature variation decreases.

In this paper, the influence of single walled carbon nanotube (SWCNT) on the series resistance (R_s) of Rose Bengal (RB) and Methyl Red (MR) dye-based organic diodes has been studied. It has been revealed from experimental results that SWCNT has a significant effect on R_s. The values of R_s are measured from current–voltage (I–V) characteristics and also by utilizing the Cheung method. Obtained values from the Cheung method have been verified using H(I)–I plots for all dye-based devices. The extracted values using these two processes show a good consistency with each other. It is observed that R_s is reduced significantly by incorporating SWCNT for both dyes. The estimated amounts of reduction of R_s using SWCNT are 76.08% and 64.23% obtained from the I–V relationship whereas the value of R_s shows a reduction of 83.5% and 67.1% when measured by using the Cheung method for RB and MR dyes respectively. The ideality factor and barrier height of the diodes have also been extracted. The ideality factor has decreased with incorporation of SWCNT. A reduction in barrier height for the devices has also been observed in the presence of SWCNT.

This paper presents a blended analytical electrical–thermal model for steady state thermal analysis of through-silicon-via (TSV) in three-dimensional (3D) integrated circuits. The proposed analytical model is validated by the commercial FEM tool—COMSOL. The comparison between the results of the proposed analytical formulas and COMSOL shows that the proposed formulas have very high accuracy with a maximum error of 0.1%. Based on the analytical model, the temperature performance of TSV is studied. Design guide lines of TSV are also given as: (1) the radius of the TSV increases, the resistance decreases and the temperature can be increased; (2) the thicker the dielectric layer, the higher the temperature; (3) compared with carbon nanotube, the Cu enlarges the temperature by 34 K, and the W case enlarges the temperature by 41 K.

In this work, the impact of well doping and corresponding body bias on UTBB MOSFETs is investigated. The ability of threshold voltage adjustment is evaluated. The results indicate that well doping can change the threshold voltage both of the N and P channel UTBB MOSFETs. The maximum amplitude for a typical 26 nm gate length device is about 100 mV, and these correspond to the cases of devices with an inverse type of high concentration dopant. The body bias adjusts the threshold voltage at a rate of 100–140 mV/V for the UTBB MOSFETs with a well. By optimizing well doping and body biasing, multi-threshold-voltage UTBB MOSFETs can be designed and optimized for lower power application.

High electron mobility transistors (HEMT) have the potential to be used as high-sensitivity and real-time biosensors. HEMT biosensors have great market prospects. For the application of HEMT biosensors, the electric properties consistency of the inter-chip performance have an important influence on the stability and repeatability of the detection. In this research, we fabricated GaAs/AlGaAs HEMT biosensors of different epitaxial structures and device structures to study the electric properties consistency. We study the relationship between channel size and consistency. We investigated the distribution of device current with location on 2 inch GaAs wafer. Based on the studies, the optimal device of a GaAs HEMT biosensor is an A-type epitaxial structure, and a U-type device structure, L = 40 μm, W = 200 μm.

Based on the effective mass approximation, the Schrödinger equation and Poisson equation in GaAs/ Al_xGa_1−xAs multi-quantum wells (MQWs) are self-consistently solved to obtain the wave functions and energy levels of electrons in the conduction band for the ground first excited state by considering a lateral electric field (LEF). Then, the effects of size, ternary mixed crystal, doping concentration, and temperature on linear and nonlinear intersubband optical absorption coefficients (IOACs), and refractive index changes (RICs) due to the transition between ground states and the first excited states of electrons are discussed based on Fermi’s golden rule. The results show that, under a fixed LEF, with increase of Al composition and doping concentration, the IOACs produce a red shift. With increases of both widths of the wells and barriers IOACs appear as blue shifts and their amplitudes increase, but the barrier width change is much more important to affect nonlinear IOACs, whereas increasing the temperature results in a blue shift first and then a red shift of IOACs. When the other parameters are fixed but there is an increase in the LEF, IOACs occur with a blue shift, and the RICs have similar properties.

In this paper, we present the drain current modulation for an HEMT using the TCAD SILVACO simulation tool with a drift–diffusion model at ambient temperature. The obtained results show that the decreases of substrate energies induce the decreasing of the obtained drain current similarly to the transconductance, which described the device due to increasing the transferred electrons concentration towards the substrate region, consequently to increase the molar fraction where the concentration of transferred electrons increases from 49 × 10¹⁹ to 65 × 10¹⁹ cm⁻³ when the molar fraction increases from 0.1 to 0.9. On the other hand, the decrease of molar fraction from 0.9 to 0.1 induces the increasing of drain current by 63%, where it increases from 1.1 mA/mm to 3 mA/mm at V_gs = 0.6 V and V_ds = 1 V . This fact leads to ensuring the possibility of using the obtained results of this work related to drain current for producing performances devices that brings together the AC characteristics of HEMT with a weak drain current, which is important in the bioengineering domain.

The spin-dependent tunneling of light holes and heavy holes was analysed in a symmetrical heterostructure with externally applied electric and magnetic fields. The effects of the applied bias voltage, magnetic field and reverse bias were discussed for the polarization efficiency of light holes and heavy holes. The current density of spin-up and spin-down light holes increases as the bias voltage increases and reaches the saturation, whereas the current density of spin-up heavy holes is almost negligible. The applied bias voltage and the magnetic field highly influence the energy of resonance polarization, polarization efficiency, and the current density of heavy holes more than for the light holes.

Vertical cavity surface emitting lasers (VCSELs) are widely used in optical communications and optical interconnects due to their advantages of low threshold, low power consumption and so on. Wet nitrogen oxidation technology, which utilizes H₂O molecules to oxidize the Al_0.98Ga_0.02As, is used for electrical and optical mode confinement. In this paper, the effects of oxidation time, oxidation temperature and oxidation anisotropy on the oxidation rate are explored and demonstrated. The ratio of oxidation rate on [0–11] to [011] crystal orientation is defined as oxidation anisotropy coefficient, which decreases with the increase of oxidation temperature and oxidation time. In order to analyze the effect of the oxidation anisotropy on the VCSEL performance, an oxide-aperture of the VCSELs with two difference shapes is designed and then fabricated. The static performance of these fabricated VCSELs has been measured, whose threshold current ratio ~ 0.714 is a good agreement with that of the theoretical calculation value ~ 0.785. Our research on wet nitrogen oxidation and its anisotropy serves as an important reference in the batch fabrication of large-area VCSELs.

An amorphous Ge (a-Ge) intermediate layer is introduced into the Si bonded interface to lower the annealing temperature and achieve good electrical characteristics. The interface and electrical characteristics of n-Si/n-Si and p-Si/n-Si junctions manufactured by low-temperature wafer bonding based on a thin amorphous Ge are investigated. It is found that the bubble density tremendously decreases when the a-Ge film is not immersed in DI water. This is due to the decrease of the –OH groups. In addition, when the samples are annealed at 400 °C for 20 h, the bubbles totally disappear. This can be explained by the appearance of the polycrystalline Ge (absorption of H₂) at the bonded interface. The junction resistance of the n-Si/n-Si bonded wafers decreases with the increase of the annealing temperature. This is consistent with the recrystallization of the a-Ge when high-temperature annealing is conducted. The carrier transport of the Si-based PN junction annealed at 350 °C is consistent with the trap-assisted tunneling model and that annealed at 400 °C is related to the carrier recombination model.

In this paper, the main content revolves round the on-state characteristics of the variation of a lateral width (VLW) LDMOS device. A three-dimensional numerical analysis is performed to investigate the specific on-resistance of the VLW LDMOS device, the simulation results are in good agreement with the analytical calculation results combined with device dimensions. This provides a theoretical basis for the design of devices in the future. Then the self-heating effect of the VLW structure with a silicon-on-oxide (SOI) substrate is compared with that of a silicon carbide (SiC) substrate by 3D thermoelectric simulation. The electrical characteristic and temperature distribution indicate that taking into account the SiC as the substrate can mitigate the self- heating penalty effectively, alleviating the self heating effect and improving reliability.

Slow and smooth etching of gallium nitride (GaN) by BCl₃/Cl₂-based inductively coupled plasma (ICP) is investigated in this paper. The effects of etch parameters, including ICP power, radio frequency (RF) power, the flow rate of Cl₂ and BCl₃, on GaN etch rate and etch surface roughness RMS are discussed. A new model is suggested to explain the impact mechanism of the BCl₃ flow rate on etch surface roughness. An optimized etch result of a slow and smooth etch surface was obtained; the etch rate and RMS were 0.36 Å/s and 0.9 nm, respectively.

The design and fabrication results of a 4-port digital isolator based on an on-chip transformer for galvanic isolation are presented. An ON–OFF keying modulation scheme is used to transmit the digital signal. The proposed digital isolator is fabricated by the 0.18 μm CMOS process. A test chip can achieve a 1 MHz signal bandwidth, a 40 ns propagation delay, a 35.5 mW input power and a 50 mA drive output current. The proposed digital isolator is pin-compatible, of small volume and low power replacement for the common 4-port optocoupler.

A high performance sample-and-hold (S/H) circuit used in a pipelined analog-to-digital converter (ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit. A gain-boosted folded cascode operational transconductance amplifier (OTA) with a DC gain of 90 dB and a GBW of 738 MHz was designed. A low supply voltage bootstrapped switch was used to improve the linearity of the S/H circuit. With these techniques, the designed S/H circuit can reach 94 dB SFDR for a 48.9 MHz input frequency with 100 MS/s sampling rate. Measurement results of a 14-bit 100-MS/s pipeline ADC with designed S/H circuit are presented.

In this paper we have studied the influence of design and process variations on the electrical performance of SiC Schottky diodes. On the design side, two design variations are used in the active cell of the diode (segment design and stripe design). In addition there are two more design variations employed for edge termination of the diodes, namely FLR and JTE. On the process side, some diodes have gone through the N₂O annealing step. The segment design resulted in lower V_F of diodes and the FLR design turned out to be a better choice for blocking voltages, in reverse bias conditions. N₂O annealing has a detrimental effect on the diodes’ blocking performance with the JTE termination design: it degrades the blocking capability of the diodes significantly.

Reliability issues of flash memory are becoming increasingly significant with the shrinking of technology nodes. Among them, erase time degradation is an issue that draws the attention of academic and industry researchers. In this paper, causes of the " erase time degradation” are exhaustively analyzed, with proposals for its improvement presented, including a low stress program/erase scheme with a staircase pulse and disturb-immune array bias condition. Implementation of the optimized circuit structure is verified in a 128 Mb SPI NOR Flash memory chip, which is fabricated on a SMIC 65 nm ETOX process platform. Testing results indicate a degradation of the sector erase time from 10.67 to 104.9 ms after 10⁵ program/erase cycles, which exhibits an improvement of approximately 100 ms over conventional schemes.

The nonlinear resistance characteristics of microcavity dielectric barrier discharge are mainly studied in the paper. A simulation model of microcavity dielectric barrier discharge is herein built to study the relationship between voltage and current in the process of discharge, and thus its I–V characteristic curve can be obtained. The I–V characteristics of the memristor are analyzed and compared with the I–V characteristics of the dielectric barrier discharge; it can be found that the I–V characteristics of the microcavity dielectric barrier discharge are similar to the characteristics of the memristor by analyzing them. The memory characteristics of microcavity dielectric barrier discharge are further analyzed.

In this study, the effect of double superlattices on GaN-based blue light-emitting diodes (LEDs) is analyzed numerically. One of the superlattices is composed of InGaN/GaN, which is designed before the multiple quantum wells (MQWs). The other one is AlInGaN/AlGaN, which is inserted between the last QB (quantum barriers) and p-GaN. The crucial characteristics of double superlattices LEDs structure, including the energy band diagrams, carrier concentrations in the active region, light output power, internal quantum efficiency, respectively, were analyzed in detail. The simulation results suggest that compared with the conventional AlGaN electron-blocking layer (EBL) LED, the LED with double superlattices has better performance due to the enhancement of electron confinement and the increase of hole injection. The double superlattices can make it easier for the carriers tunneling to the MQWs, especially for the holes. Furthermore, the LED with the double superlattices can effectively suppress the electron overflow out of multiple quantum wells simultaneously. From the result, we argue that output power is enhanced dramatically, and the efficiency droop is substantially mitigated when the double superlattices are used.

In this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable methodology is proposed and integrated in 32-bit DLX reduced instruction set computer (RISC) processor on a single silicon chip. The proposed methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self-testing to detect temporary faults.

This paper proposes a high-performance pulse-width modulation (PWM) AC/DC controller, which can drive a high-voltage (HV) 650-V power metal-oxide-semiconductor field-effect Transistor (MOSFET) in typical applications of adapters in portable electronic devices. In order to reduce the standby power consumption and improve the response speed in the start-up state, an improved under voltage lockout (UVLO) circuit without a voltage reference source or comparator is adopted. The AC/DC controller is fabricated using a 40-V 0.8-μm one-poly two-metal (1P2M) CMOS process, and it only occupies 1410 × 730 μm². A 12 V/2 A flyback topology for quick-charge application is illustrated as the test circuit, which is currently one of the most advanced power adapters in use. Test values show that the turn-on and the turn-off threshold voltages are 19.318 and 8.01 V, respectively. A high hysteresis voltage of 11.308 V causes the value of the power-charging capacitor to decrease to as low as 1 μF to reduce production cost. In addition, the start-up current of 2.3 μA is extremely small, and is attributed to a reduction in the system's standby power consumption. The final test results of the overall system are proven to meet the Energy Star VI standard. The controller has already been mass produced for industrial applications.

The frequency stability of a three-dimensional (3D) vacuum encapsulated very high frequency (VHF) disk resonator is systematically investigated. For eliminating the parasitic effect caused by the parasitic capacitance of the printed circuit board (PCB), a negating capacitive compensation method was developed. The testing results implemented at 25 °C for 240 h for the long-term stability indicates that the resonant frequency variation remained within ±1 ppm and the noise floor derived from Allan Deviation was 26 ppb, which is competitive with the conventional quartz resonators. The resonant frequency fluctuation of 1.5 ppm was obtained during 200 temperature cycling between −40 and 85 °C.

The frequency stability of free-running semiconductor lasers is influenced by several factors, such as driving current and external operating environment. The frequency stabilization of laser has become an international research hotspot in recent years. This paper reviews active frequency stabilization technologies of laser diodes and elaborates their principles. Based on differences of frequency discrimination curves, these active frequency stabilization technologies are classified into three major types, which are harmonic frequency stabilization, Pound-Drever-Hall (PDH) technology and curve subtraction frequency stabilization. Further, merits and demerits of each technology are compared from aspects of frequency stability and structure complexity. Finally, prospects of frequency stabilization technologies of semiconductor lasers are discussed in detail. Combining several of these methods are future trends, especially the combination of frequency stabilization of F–P cavity. And PID electronic control for optimizing the servo system is generally added in the methods mentioned above.

High speed VCSELs are important optical devices in short-reach optical communication links and interconnects because of their low cost and high modulation speeds. In this paper, the impact of damping on the their static and dynamic characteristics is analyzed and demonstrated. Through the shallow corrosion of the top layer DBR, the VCSELs with different damping is designed and fabricated. With the increase of the surface etch depth from 0 to ~55 nm for 9 μm oxide-aperture VCSEL, the K factor related with the damping is reduced from 0.31 to 0.23 ns⁻¹. When the etch depth of the VCSEL with 9 μm oxide-aperture is decreased to ~25 nm, output power is increased from 4.03 to 4.70 mW and small signal modulation bandwidth is also increased from 15.46 to 16.37 GHz. It shows that there is a tradeoff between damping and differential gain for improving modulation speed.

This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS (BCD) technology for implantable medical devices. Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm².

A three-dimensional thermal analysis of GaN HEMTs on diamond substrate is investigated using the finite element method. The diamond substrate thickness, area and shape, transition layer thickness and thermal conductivity of the transition layer are considered and treated appropriately in the numerical simulation. The temperature distribution and heat spreading paths are investigated under different conditions and the results indicate that the existence of the transition layer causes an increase in the channel temperature and the thickness, area and shape of the diamond substrate have certain impacts on the channel temperature too. Channel temperature reduces with increasing diamond substrate thickness and area but with a decreasing trend, which can be explained by the saturation effects of the diamond substrate. The shape of diamond substrate also affects the temperature performance of GaN HEMTs, therefore, to achieve a favorable heat dissipation effect with the settled diamond substrate area, the shape should contain as many isothermal curves as possible when the isothermal gradient is constant. The study of the thermal properties of GaN on diamond substrate is useful for the prediction of heating of high power GaN HEMTs devices and optimal designs of an efficient heat spreader for GaN HEMTs.

We present a voltage reference using a wide-band cascaded current mode differentiator, for the improved PSRR performance. Compared with the conventional references, the reference with the technique is mainly characterized by a two cascaded stages current mode signal differentiator. In the differentiator, a zero OTA G_m is proposed, to achieve the wide-band differential characteristic. With the technique, the PSRR beyond the pole’s corresponding frequency can be significantly improved with the minimum supply voltage only about V_{GS_PMOS} + (V_{GS_NMOS} − V_TH). Fabricated with a 0.18 μm CMOS process, with the 0.9 V supply voltage, the PSRR @ 20 MHz of the reference is achieved at −54 dB. Moreover, the power dissipation is 19 μW.

This review paper gives an outline of the recent research progress and challenges of 2D TMDs material MoS₂ based device, that leads to an interesting path towards approaching the electronic applications due to its sizeable band gap. This review presents the improvement of MoS₂ material as an alternate to a silicon channel in a transistor with its excellent energy band gap, thermal conductivity, and exclusive physical properties that are expected to draw attention to focusing on semiconducting devices for most futuristic applications. We discuss the band structure of MoS₂ for a different number of layers with its structure, and various synthesis techniques of the MoS₂ layer are also reviewed. The MoS₂ based field effect transistor has attracted a great deal of attention due to its excellent properties such as mobility, on/off current ratio, and maximum on-current of the devices. The transition of mobility as a function of temperature and thickness dependence are also discussed. However, the mobility of MoS₂ material is large in bulk form and lower in monolayer form. The use of a high-k gate dielectric in MoS₂ FET is used to enhance the mobility of the device. Different metal contact engineering and different doping techniques were deployed to achieve low contact resistance. This review paper focuses on various aspects of layered TMDs material MoS₂ based field effect transistors.

An ultralow specific on-resistance high-k LDMOS with vertical field plate (VFP HK LDMOS) is proposed in this paper. The high-k dielectric trench and highly doped interface N⁺ layer are made in bulk silicon to reduce the surface field of the drift region in the VFP HK LDMOS. The gate vertical field plate (VFP) pinning in the high-k dielectric trench can modulate the bulk electric field. The high-k dielectric not only provides polarized charges to assist depletion of the drift region, so that the drift region and high-k trench maintain charge balance adaptively, but also can fully assist in depleting the drift region to increase the drift doping concentration and reshape the electric field to avoid premature breakdown. Compared with the conventional structure, the VFP HK LDMOS has the breakdown voltage of 629.1 V at the drift length of 40 μm and the specific on-resistance of 38.4 mΩ·cm² at the gate potential of 15 V. Then the power figure of merit is 10.31 MW/cm².

The GaSb-based distributed Bragg reflection (DBR) diode laser with 23rd-order gratings have been fabricated by conventional UV lithography and inductively coupled plasma (ICP) etching. The ICP etching conditions were optimized and the relationship among etching depth, duty ratio and side-mode suppression ratio (SMSR) was studied. The device with a ridge width of 100 μm, gratings period of 13 μm and etching depth of 1.55 μm as well as the duty ratio of 85% was fabricated, its maximum SMSR reached 22.52 dB with uncoated cavity facets under single longitudinal operation mode at room temperature.

In this paper, the double barrier quantum well (DBQW) resonant tunneling diode (RTD) structure made of SiGeSn/GeC/SiGeSn alloys grown on Ge substrate is analyzed. The tensile strained Ge_1−zC_z on Si_1−x−yGe_xSn_y heterostructure provides a direct band gap type I configuration. The transmission coefficient and tunneling current density have been calculated considering single and multiple quantum wells. A comparative study of tunnelling current of the proposed structure is done with the existing RTD structure based on GeSn/SiGeSn DBH. A higher value of the current density for the proposed structure has been obtained.

In this paper, we propose a reliable asymmetric dual-k spacer with SiC source/drain (S/D) pocket as a stressor for a Si channel. This enhances the device performance in terms of electron mobility (eMobility), current driving capabilities, transconductance (G_m) and subthreshold slope (SS). The improved performance is an amalgamation of longitudinal tensile stress along the channel and reduced series resistance. We analysed the variation in drive current for different values of carbon (C) mole fraction y in Si_1−yC_y. It is found that the mole fraction also helps to improve device lifetime, performance enhancement also pointed by transconductance variation with the gate length. All the simulations are performed in the 3-D Sentaurus TCAD tool. The proposed device structure achieved I_ON = 2.17 mA/μm for Si_0.3C_0.7 and found that Si_0.5C_0.5 is more suitable for the perspective of a process variation effect for 14 nm as the gate length. We introduce reliability issues and their solutions for Si_1−yC_y FinFET for the first time.

Analytical models are presented for a negative capacitance double-gate tunnel field-effect transistor (NC DG TFET) with a ferroelectric gate dielectric in this paper. The model accurately calculates the channel potential profile by solving the Poisson equation with the Landau–Khalatnikov (LK) equation. Moreover, the effects of the channel mobile charges on the potential are also taken into account. We also analyze the dependences of the channel potential and the on-state current on the device parameters by changing the thickness of ferroelectric layer, ferroelectric material and also verify the simulation results accord with commercial TCAD. The results show that the device can obtain better characteristics when the thickness of the ferroelectric layer is larger as it can reduce the shortest tunneling length.

In the current research, the proposed technique to synthesise poly {(2,5-diyl pyrrole) (2-pyrrolyl methine)} (PPPM) copolymer by condensation of pyrrole and pyrrole-2- carboxaldehyde monomers catalyzed by Maghnite-H⁺ is introduced. The protons are exchanged with Maghnite-H⁺, which is available in the form of a montmorillonite silicate clay sheet. The effect of several parameters such as time and temperature of copolymerization, [pyrrole]/[pyrrole-2-carboxaldehyde] molar ratio, amount of Maghnite-H⁺, and solvent on the produced poly (2,5-diyl pyrrole-2- pyrrolyl methine) semiconductor copolymer material (yield%) was investigated. The synthesized PPPM copolymer was characterized using nuclear magnetic resonance, Fourier transform infrared, and ultraviolet-visible spectroscopy. The results show that the synthesized copolymer using the copolymerization technique is a real organic copolymer consisting of two monomers units (i.e, pyrrole and pyrrole- 2-carboxaldehyde). Also, the synthesized copolymer is more soluble than polypyrrole in most of the commonly used organic solvents. Hence, copolymerization of pyrrole with pyrrole-2- carboxaldehyde will overcome the insolubility of polypyrrole. In addition, the resultant copolymer exhibits good film formability. The produced copolymer has several potential applications in the field of rechargeable batteries, sensors, capacitors, light emitting diodes, optical displays, and solar cells.