The three-dimensional hierarchical CuO and Au nanoparticles were synthesized by the hydrothermal method, respectively. The hierarchical CuO and the Au nanoparticles samples were characterized by X-ray diffraction and scanning electronic microscope, respectively. The as-synthesized CuO was assembled regularly from the nanosheets with thickness of 100 nm. The size of Au nanoparticles ranged from 50 to 200 nm. The hierarchical CuO gas sensors modified by different concentration of gold were fabricated. All the Au-loaded CuO gas sensors enhanced the response to ethanol and xylene while reducing the response to methanol, acetone, and formaldehyde. The results indicate that the Au nanoparticles prepared with PVP as surfactant can improve the selectivity of CuO gas sensors to ethanol gas for other common organic volatile gases. The improvement of gas sensing is mainly attributed to the different catalytic efficiency of the Au nanoparticles for different reactions. Meanwhile, the related mechanisms are discussed.

GaN-based continuous-wave operated blue-violet laser diodes (LDs) with long lifetime are demonstrated, which are grown on a c-plane GaN substrate by metal organic chemical vapor deposition with a 10 × 600 μm² ridge waveguide structure. The electrical and optical characteristics of a blue-violet LD are investigated under direct-current injection at room temperature (25 °C). The stimulated emission wavelength and peak optical power of the LD are around 413 nm and over 600 mW, respectively. In addition, the threshold current density and voltage are as small as 1.46 kA/cm² and 4.1 V, respectively. Moreover, the lifetime is longer than 1000 hours under room-temperature continuous-wave operation.

Benzotriazole (BTA), an anticorrosion agent of slurry, is the main organic pollutant remaining after CMP of multilayer copper wiring, and also the main removal object of post CMP cleaning. The adsorption of BTA onto the copper could form a dense Cu-BTA film, which makes the copper surface strongly passivated. According to this characteristic, quantitative analysis of BTA residue after cleaning is carried out by contact angle measurement and electrochemical measurement in this paper. A scanning electron microscope (SEM) with EDX was used to observe and analyze the BTA shape and elements. The efficiencies of organic alkali and inorganic alkali on the removal of BTA were studied. The corresponding reaction mechanism was also analyzed. The results show that the adsorption structure of Cu-BTA cannot be destroyed in an alkaline environment with a pH less than 10; the effect of BTA removal by inorganic alkali is worse than that of the organic amine alkali with the coordination structure under the same pH environment; the FA/O II chelating agent with the fraction of 200 ppm can effectively remove BTA residue on the surface of copper wafer.

The evolution of the traditional metal oxide field effect transistor (MOSFET) from planar single gate devices into 3D multiple gates has led to higher package density and high current drive. However, due to continuous scaling and as a consequent close proximity between source and drain in the nano-regime, these multigate devices have been found to suffer from performance degrading short channel effects (SCEs). In this paper, a three dimensional analytical model of a trigate MOSFET incorporating non-conventional structural techniques like silicon-on-insulator, gate and channel engineering in addition to gate oxide stack is presented. The electrostatic integrity and device capability of suppressing SCEs is investigated by deriving the potential distribution profile using the three dimensional Poisson’s equation along with suitable boundary conditions. The other device parameters like threshold voltage and subthreshold swing are produced from the surface potential model. The validity of the proposed structure is established by the close agreement among the results obtained from the analytical model and simulation results.

A wideband CMOS power amplifier with high gain and excellent gain flatness for X–Ku-band radar phased array is proposed in this paper. Excellent gain flatness is achieved with transformer based matching networks (TMNs), in which the gain fluctuation of an inter-stage matching network can be compensated by the proposed design methods. The circuit is fabricated in the TSMC 65 nm RF CMOS process. The proposed technique is verified by the measurement results, which show that the wideband PA achieves gain of 21–22.5 dB with only ±0.75 dB gain fluctuation and 13–14.6 dBm flat output power between 7.5 and 15.5 GHz, and a little more ripple in the rest of the X–Ku band due to the inaccuracy of passive modelling at high frequency. The circuit delivers saturated and 1 dB-compressed output power of 14.6 and 11.3 dBm respectively at 13 GHz, for a maximal power-added efficiency (PAE) of 23%.

Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study, through glass vias (TGVs) are used to implement 3-D inductors for minimal footprint and large quality factor. Using the inductors and parallel plate capacitors, a compact 3-D Wilkinson power divider is designed and analyzed. Compared with some reported power dividers, the proposed TGV-based circuit has an ultra-compact size and excellent electrical performance.

Although tin halide perovskite has shown excellent photoelectric performance, its efficiency of solar cell is low compared with that of lead halide. In order to enhance the efficiency of tin halide perovskite solar cell, a deep understanding of the role of the defects in the perovskite absorption layer and at the electron transport layer (ETL)/absorber or absorber/hole transport layer (HTL) interface is very necessary. In this work, the planar heterojunction-based CH₃NH₃SnI₃ perovskite solar cells were simulated with the SCAPS-1D program. Simulation results revealed a great dependence of device efficiency on defect density and interface quality of the perovskite absorber. The defect density at the front interface is critical for high efficiency, and the polarity of the interface charge has a different impact on the device efficiency. Strikingly, an efficiency over 29% was obtained under the moderate simulation conditions.

Ga₂O₃ metal–oxide–semiconductor field-effect transistors (MOSFETs) with high-breakdown characteristics were fabricated on a homoepitaxial n-typed β-Ga₂O₃ film, which was grown by metal organic chemical vapor deposition (MOCVD) on an Fe-doped semi-insulating (010) Ga₂O₃ substrate. The structure consisted of a 400 nm unintentionally doped (UID) Ga₂O₃ buffer layer and an 80 nm Si-doped channel layer. A high k HfO₂ gate dielectric film formed by atomic layer deposition was employed to reduce the gate leakage. Moreover, a source-connected field plate was introduced to enhance the breakdown characteristics. The drain saturation current density of the fabricated device reached 101 mA/mm at V_gs of 3 V. The off-state current was as low as 7.1 × 10⁻¹¹ A/mm, and the drain current I_ON/I_OFF ratio reached 10⁹. The transistors exhibited three-terminal off-state breakdown voltages of 450 and 550 V, corresponding to gate-to-drain spacing of 4 and 8 μm, respectively.

The cleaning of copper interconnect chemical mechanical polishing (CMP) is a key process in integrated circuits (ICs) fabrication. Silicon dioxide, which is used as the abrasive material in copper CMP slurry, is considered as the main particle contamination. Abrasive particle residuals can cause device failure which need to be removed efficiently. In this paper, a type of CMP cleaner was used for particle removal using a cleaning solution consisting of FA/O II chelating agent and FA/O I surfactant. By varying the parameters of brush rotation speed, brush gap, and de-ionized water (DIW) flow rate, a series of experiments were performed to determine the best cleaning results. Atomic force microscope (AFM) measurement was used to characterise the surface morphology of the copper surface and the removal of abrasive particles. A scanning electron microscope (SEM) with EDS was used to observe and analyze the particles shape and elements. The optima parameters of CMP cleaner were obtained. Under those conditions, the abrasive silica particles were removed effectively.

The CuInGeSe₄ thin film was deposited onto n-type single crystal silicon wafers by the electron beam deposition technique. The Au/CuInGeSe₄/n-Si/Al heterojunction device has been fabricated. The structure of the CuInGeSe₄ thin film was characterized by X-ray diffraction (XRD), scanning electron microscope (SEM), and energy dispersive X-ray analysis (EDX). The dark current–voltage characteristics of the Au/CuInGeSe₄/n-Si/Al heterojunction diode have been studied at a temperature range of 303–383 K. Also, the photovoltaic properties were examined at different illumination intensities. The capacitance–voltage characteristics of the CuInGeSe₄/n-Si heterojunction were studied at different temperatures in the dark.

A hot spot is a reliability problem in photovoltaic (PV) modules where a mismatched or shaded cell heats up significantly and degrades the PV module output power performance. High PV cell temperature due to a hot spot can damage the cell encapsulate and lead to second breakdown, which both cause permanent damage to the PV module. In present systems, bypass diodes are used to mitigate the hot spot problem. In this work, five commercial polysilicon PV modules configured with different numbers of bypass diodes are used to study the influence of bypass diodes on the reverse bias voltage of a shaded cell and the resulting hot spot phenomenon. The reverse bias voltage of the shaded cell, and the hot spot probability and severity decrease as the number of bypass diodes increases. Negative terminal voltage of a shaded cell accompanied by a switched-off bypass diode are the necessary condition for hot spot generation. In an extreme case where each cell has an individual bypass diode in a PV module, it still cannot avoid the hazards of a hot spot under the shading areas of 5–7 cm², but the probability of a hot spot is reduced to a minimum of 0.41%.

To meet the demand for high on-chip network performance, flexible routing algorithms supplying path diversity and congestion alleviation are required. We propose a CAOE-FA router as a combination of congestion-awareness and fair arbitration. Buffer occupancies from downstream neighbors are collected to indicate the congestion levels, among the candidate outputs permitted by the odd-even (OE) turn model, the lightest loaded direction is selected; fair arbitration is employed for the condition of the same congestion level to replace random selection. Experimental results show that the CAOE-FA can reduce the average packet latency by up to 22.18% and improve the network throughput by up to 68.58%, with ignorable price of hardware cost.

The performance of the power amplifier determines the detection capability of 77 GHz automotive radar, and the bias circuit is one of the most important parts of a silicon-germanium power amplifier. In this paper, we discussed and designed an on-chip bias circuit based on a silicon-germanium heterojunction bipolar transistor, which is used for the W-band silicon–germanium power amplifier. Considering the low breakdown voltage and the correlation between characteristic frequency and bias current density of the silicon-germanium heterojunction bipolar transistor, the bias circuit is designed to improve the breakdown voltage of the power amplifier and meet the W band characteristic frequency at the same time. The simulation results show that the designed bias circuit can make the amplifier operate normally from −40 to 125 °C. In addition, the output power and smooth controllability of the power amplifier can be adjusted by controlling the bias circuit.

We have theoretically studied current self-oscillations in double-layer graphene n+nn+ diodes driven by dc bias with the help of a time-dependent hydrodynamic model. The current self-oscillation results from resonant tunneling in the double-layer graphene structure. A detailed investigation of the dependence of the current self-oscillations on the applied bias has been carried out. The frequencies of current self-oscillations are in the terahertz (THz) region. The double-layer graphene n⁺nn⁺ device studied here may be presented as a THz source at room temperature.

Φ55 × 15 mm² CdS bulk single crystal with high infrared transmittance was grown by physical vapor transport. The single crystal has a consistent structure from top to bottom, which was confirmed by X-ray diffraction. The (002) full-width at half-maximum of the X-ray diffraction was measured to be 60.00 arcsec, indicating a good quality of the structure. Hall mobility, specific resistivity, and carrier concentration for the top and bottom of the crystal were observed as well. Transmittance for the CdS single crystal was measured to be higher than 70% from 2.5 to 4.5 µm, making the single crystal an important candidate for infrared window materials. Furthermore, the absorption mechanism of the CdS single crystal was analyzed.

In this investigation, visible photocatalytic dye decomposition is carried out with compound semiconductor nanoparticles of zinc orthotitanate (Zn₂TiO₄). These nanoparticles were grown by the solid state reaction method and characterized by field emission scanning electron microscopy, transmission electron microscopy, X-ray diffraction, diffuse reflectance spectroscopy, photoluminescence study, and Brunauer–Emmett–Teller (BET) study. The BET surface area of the Zn₂TiO₄ nanoparticles was found to be 8.78 m²/g. The photocatalytic activity is carried out by using a 500 W halogen light source having a spectrum in the range of 450 to 860 nm and the reaction kinetics was found to be the pseudo first order. The reaction rate constant was found to be 0.069 min⁻¹. Discussion is given on the possible mechanism of the observed visible photocatalytic dye decomposition activity. The cost of the material used is very low so it could be very useful for visible photocatalytic dye decomposition.

The frequency stability of free-running semiconductor lasers is influenced by several factors, such as driving current and external operating environment. The frequency stabilization of laser has become an international research hotspot in recent years. This paper reviews active frequency stabilization technologies of laser diodes and elaborates their principles. Based on differences of frequency discrimination curves, these active frequency stabilization technologies are classified into three major types, which are harmonic frequency stabilization, Pound-Drever-Hall (PDH) technology and curve subtraction frequency stabilization. Further, merits and demerits of each technology are compared from aspects of frequency stability and structure complexity. Finally, prospects of frequency stabilization technologies of semiconductor lasers are discussed in detail. Combining several of these methods are future trends, especially the combination of frequency stabilization of F–P cavity. And PID electronic control for optimizing the servo system is generally added in the methods mentioned above.

In this paper, we present the drain current modulation for an HEMT using the TCAD SILVACO simulation tool with a drift–diffusion model at ambient temperature. The obtained results show that the decreases of substrate energies induce the decreasing of the obtained drain current similarly to the transconductance, which described the device due to increasing the transferred electrons concentration towards the substrate region, consequently to increase the molar fraction where the concentration of transferred electrons increases from 49 × 10¹⁹ to 65 × 10¹⁹ cm⁻³ when the molar fraction increases from 0.1 to 0.9. On the other hand, the decrease of molar fraction from 0.9 to 0.1 induces the increasing of drain current by 63%, where it increases from 1.1 mA/mm to 3 mA/mm at V_gs = 0.6 V and V_ds = 1 V . This fact leads to ensuring the possibility of using the obtained results of this work related to drain current for producing performances devices that brings together the AC characteristics of HEMT with a weak drain current, which is important in the bioengineering domain.

The spin-dependent tunneling of light holes and heavy holes was analysed in a symmetrical heterostructure with externally applied electric and magnetic fields. The effects of the applied bias voltage, magnetic field and reverse bias were discussed for the polarization efficiency of light holes and heavy holes. The current density of spin-up and spin-down light holes increases as the bias voltage increases and reaches the saturation, whereas the current density of spin-up heavy holes is almost negligible. The applied bias voltage and the magnetic field highly influence the energy of resonance polarization, polarization efficiency, and the current density of heavy holes more than for the light holes.

High speed VCSELs are important optical devices in short-reach optical communication links and interconnects because of their low cost and high modulation speeds. In this paper, the impact of damping on the their static and dynamic characteristics is analyzed and demonstrated. Through the shallow corrosion of the top layer DBR, the VCSELs with different damping is designed and fabricated. With the increase of the surface etch depth from 0 to ~55 nm for 9 μm oxide-aperture VCSEL, the K factor related with the damping is reduced from 0.31 to 0.23 ns⁻¹. When the etch depth of the VCSEL with 9 μm oxide-aperture is decreased to ~25 nm, output power is increased from 4.03 to 4.70 mW and small signal modulation bandwidth is also increased from 15.46 to 16.37 GHz. It shows that there is a tradeoff between damping and differential gain for improving modulation speed.

Vertical cavity surface emitting lasers (VCSELs) are widely used in optical communications and optical interconnects due to their advantages of low threshold, low power consumption and so on. Wet nitrogen oxidation technology, which utilizes H₂O molecules to oxidize the Al_0.98Ga_0.02As, is used for electrical and optical mode confinement. In this paper, the effects of oxidation time, oxidation temperature and oxidation anisotropy on the oxidation rate are explored and demonstrated. The ratio of oxidation rate on [0–11] to [011] crystal orientation is defined as oxidation anisotropy coefficient, which decreases with the increase of oxidation temperature and oxidation time. In order to analyze the effect of the oxidation anisotropy on the VCSEL performance, an oxide-aperture of the VCSELs with two difference shapes is designed and then fabricated. The static performance of these fabricated VCSELs has been measured, whose threshold current ratio ~ 0.714 is a good agreement with that of the theoretical calculation value ~ 0.785. Our research on wet nitrogen oxidation and its anisotropy serves as an important reference in the batch fabrication of large-area VCSELs.

An amorphous Ge (a-Ge) intermediate layer is introduced into the Si bonded interface to lower the annealing temperature and achieve good electrical characteristics. The interface and electrical characteristics of n-Si/n-Si and p-Si/n-Si junctions manufactured by low-temperature wafer bonding based on a thin amorphous Ge are investigated. It is found that the bubble density tremendously decreases when the a-Ge film is not immersed in DI water. This is due to the decrease of the –OH groups. In addition, when the samples are annealed at 400 °C for 20 h, the bubbles totally disappear. This can be explained by the appearance of the polycrystalline Ge (absorption of H₂) at the bonded interface. The junction resistance of the n-Si/n-Si bonded wafers decreases with the increase of the annealing temperature. This is consistent with the recrystallization of the a-Ge when high-temperature annealing is conducted. The carrier transport of the Si-based PN junction annealed at 350 °C is consistent with the trap-assisted tunneling model and that annealed at 400 °C is related to the carrier recombination model.

In this paper, the main content revolves round the on-state characteristics of the variation of a lateral width (VLW) LDMOS device. A three-dimensional numerical analysis is performed to investigate the specific on-resistance of the VLW LDMOS device, the simulation results are in good agreement with the analytical calculation results combined with device dimensions. This provides a theoretical basis for the design of devices in the future. Then the self-heating effect of the VLW structure with a silicon-on-oxide (SOI) substrate is compared with that of a silicon carbide (SiC) substrate by 3D thermoelectric simulation. The electrical characteristic and temperature distribution indicate that taking into account the SiC as the substrate can mitigate the self- heating penalty effectively, alleviating the self heating effect and improving reliability.

Slow and smooth etching of gallium nitride (GaN) by BCl₃/Cl₂-based inductively coupled plasma (ICP) is investigated in this paper. The effects of etch parameters, including ICP power, radio frequency (RF) power, the flow rate of Cl₂ and BCl₃, on GaN etch rate and etch surface roughness RMS are discussed. A new model is suggested to explain the impact mechanism of the BCl₃ flow rate on etch surface roughness. An optimized etch result of a slow and smooth etch surface was obtained; the etch rate and RMS were 0.36 Å/s and 0.9 nm, respectively.

The design and fabrication results of a 4-port digital isolator based on an on-chip transformer for galvanic isolation are presented. An ON–OFF keying modulation scheme is used to transmit the digital signal. The proposed digital isolator is fabricated by the 0.18 μm CMOS process. A test chip can achieve a 1 MHz signal bandwidth, a 40 ns propagation delay, a 35.5 mW input power and a 50 mA drive output current. The proposed digital isolator is pin-compatible, of small volume and low power replacement for the common 4-port optocoupler.

A high performance sample-and-hold (S/H) circuit used in a pipelined analog-to-digital converter (ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit. A gain-boosted folded cascode operational transconductance amplifier (OTA) with a DC gain of 90 dB and a GBW of 738 MHz was designed. A low supply voltage bootstrapped switch was used to improve the linearity of the S/H circuit. With these techniques, the designed S/H circuit can reach 94 dB SFDR for a 48.9 MHz input frequency with 100 MS/s sampling rate. Measurement results of a 14-bit 100-MS/s pipeline ADC with designed S/H circuit are presented.

In this paper we have studied the influence of design and process variations on the electrical performance of SiC Schottky diodes. On the design side, two design variations are used in the active cell of the diode (segment design and stripe design). In addition, there are two more design variations employed for the edge termination layout of the diodes, namely, field limiting ring (FLR) and junction termination extension (JTE). On the process side, some diodes have gone through an N₂O annealing step. The segment design resulted in a lower forward voltage drop (V_F) in the diodes and the FLR design turned out to be a better choice for blocking voltages, in the reverse bias. Also, N₂O annealing has shown a detrimental effect on the diodes’ blocking performance, which have JTE as their termination design. It degrades the blocking capability of the diodes significantly.

The nonlinear resistance characteristics of microcavity dielectric barrier discharge are mainly studied in the paper. A simulation model of microcavity dielectric barrier discharge is herein built to study the relationship between voltage and current in the process of discharge, and thus its I–V characteristic curve can be obtained. The I–V characteristics of the memristor are analyzed and compared with the I–V characteristics of the dielectric barrier discharge; it can be found that the I–V characteristics of the microcavity dielectric barrier discharge are similar to the characteristics of the memristor by analyzing them. The memory characteristics of microcavity dielectric barrier discharge are further analyzed.

In this study, the effect of double superlattices on GaN-based blue light-emitting diodes (LEDs) is analyzed numerically. One of the superlattices is composed of InGaN/GaN, which is designed before the multiple quantum wells (MQWs). The other one is AlInGaN/AlGaN, which is inserted between the last QB (quantum barriers) and p-GaN. The crucial characteristics of double superlattices LEDs structure, including the energy band diagrams, carrier concentrations in the active region, light output power, internal quantum efficiency, respectively, were analyzed in detail. The simulation results suggest that compared with the conventional AlGaN electron-blocking layer (EBL) LED, the LED with double superlattices has better performance due to the enhancement of electron confinement and the increase of hole injection. The double superlattices can make it easier for the carriers tunneling to the MQWs, especially for the holes. Furthermore, the LED with the double superlattices can effectively suppress the electron overflow out of multiple quantum wells simultaneously. From the result, we argue that output power is enhanced dramatically, and the efficiency droop is substantially mitigated when the double superlattices are used.

In this paper, we propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable architecture is proposed and integrated in 32-bit DLX reduced instruction set computer (RISC) processor on a single silicon chip. The proposed concurrent test methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self-testing to detect temporary faults.

InAs-based interband cascade lasers (ICLs) with InAs plasmon waveguides or InAs/AlSb superlattice (SL) waveguides were demonstrated at emission wavelengths below 4.1 μm. The threshold current densities of the lasers with SL waveguides were 37 A/cm² at 77 K in continuous wave mode. The operation temperature of these lasers reached room temperature in pulsed mode. Compared with the thick InAs n⁺⁺ plasmon cladding layer, the InAs/AlSb superlattice cladding layers have greater advantages for ICLs with wavelengths less than 4 μm even in InAs based ICLs because in the short-wavelength region they have a higher confinement factor than InAs plasmon waveguides.

In this paper a 0.6 V, 14 bit/500 Hz subthreshold inverter-based sigma–delta modulator is proposed. In the first integrator of the modulator, a bootstrap switch is used to accomplish accurate signal sampling. Without a transconductor operational amplifier (OTA), the sigma–delta modulator adopts a cascode inverter in the subthreshold region to save power consumption. The modulator is fabricated with a 0.13 μm CMOS mixed-signal process. The experiment results show that with the 0.6 V power supply it achieves a maximum SNDR of 69.7 dB and an ENOB of 11.3 bit, respectively, but only consumes 5.07 μw power dissipation.

A C-band polarization rotator-splitter based on a mode-evolution structure and an asymmetric directional coupler is proposed. The mode-evolution structure is designed in a bi-level taper through which the TM₀ mode can evolve into the TE₁ mode. Then the TE₁ mode is coupled to the TE₀ mode at the cross port using the asymmetric directional coupler. The input TE₀ mode propagates along the waveguide without mode conversion and output at the through port. From the experimental results, the extinction ratio is lower than 30 dB and the excess loss is less than 1 dB for input TE₀ mode at the whole C-band. For input TM₀ mode, the ER and the EL are, respectively, lower than −10 and 1.5 dB.

Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs (short channel effects) in sub 22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2 (conventional HfO₂ spacer SOI FinFET) and device-D3 (source/drain extended HfO₂ spacer SOI FinFET) over the device-D1 (conventional Si₃N₄ spacer SOI FinFET) at 20 nm technology node through the 3-D (dimensional) simulation process. The major performance parameters like I_on (ON current), I_off (OFF current), g_m (transconductance), g_d (output conductance), A_V (intrinsic gain), SS (sub-threshold slope), TGF = g_m/I_d (trans-conductance generation factor), V_EA (early voltage), GTFP (gain trans-conductance frequency product), TFP (tans-conductance frequency product), GFP (gain frequency product), and f_T (cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation, device-D3 and D2 give better results in terms of g_m, I_D (drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of f_T, GTFP, TFP, and GFP parameters both at low and high values of V_DS = 0.05 V and V_DS = 0.7 V respectively.

This paper proposes a fast-locking bang-bang phase-locked loop (BBPLL). A novel adaptive loop gain controller (ALGC) is proposed to increase the locking speed of the BBPLL. A novel bang-bang phase/frequency detector (BBPFD) with adaptive-mode-selective circuits is proposed to select the locking mode of the BBPLL during the locking process. Based on the detected results of the BBPFD, the ALGC can dynamically adjust the overall gain of the loop for fast-locking procedure. Compared with the conventional BBPFD, only a few gates are added in the proposed BBPFD. Therefore, the proposed BBPFD with adaptive-mode-selective circuits is realized with little area and power penalties. The fast-locking BBPLL is implemented in a 65 nm CMOS technology. The core area of the BBPLL is 0.022 mm². Measured results show that the BBPLL operates at a frequency range from 0.6 to 2.4 GHz. When operating at 1.8 GHz, the power consumption is 3.1 mW with a 0.9-V supply voltage. With the proposed techniques, the BBPLL achieves a normalized locked time of 1.1 μs @ 100 MHz frequency jump. The figure-of-merit of the fast-locking BBPLL is −334 dB.

In this work, the impact of well doping and corresponding body bias on UTBB MOSFETs is investigated. The ability of threshold voltage adjustment is evaluated. The results indicate that well doping can change the threshold voltage both of the N and P channel UTBB MOSFETs. The maximum amplitude for a typical 26 nm gate length device is about 100 mV, and these correspond to the cases of devices with an inverse type of high concentration dopant. The body bias adjusts the threshold voltage at a rate of 100–140 mV/V for the UTBB MOSFETs with a well. By optimizing well doping and body biasing, multi-threshold-voltage UTBB MOSFETs can be designed and optimized for lower power application.

This paper presents a new model to study the static performances of a GaN metal epitaxial-semiconductor field effect transistor (MESFET) based on the metal-semiconductor interface state of the Schottky junction. The I–V performances of MESFET under different channel lengths and different operating systems (pinch-off or not) have been achieved by our model, which strictly depended on the electrical parameters, such as the drain-gate capacity C_gd, the source–gate capacity C_gs, the transconductance, and the conductance. To determine the accuracy of our model, root-mean-square (RMS) errors were calculated. In the experiment, the experimental data agree with our model. Also, the minimum value of the electrical parameter has been calculated to get the maximum cut-off frequency for the GaN MESFET.

High electron mobility transistors (HEMT) have the potential to be used as high-sensitivity and real-time biosensors. HEMT biosensors have great market prospects. For the application of HEMT biosensors, the electric properties consistency of the inter-chip performance have an important influence on the stability and repeatability of the detection. In this research, we fabricated GaAs/AlGaAs HEMT biosensors of different epitaxial structures and device structures to study the electric properties consistency. We study the relationship between channel size and consistency. We investigated the distribution of device current with location on 2 inch GaAs wafer. Based on the studies, the optimal device of a GaAs HEMT biosensor is an A-type epitaxial structure, and a U-type device structure, L = 40 μm, W = 200 μm.

A novel power-on-reset (POR) circuit with simple architecture, small values of capacitances, ultra-lower power consumption, and self-adjustable delay time of reset pulse for passive UHF RFID tags is presented in this paper. A proposed delay element was adopted for the features of small capacitances and wide power supply rise time range. An inverter was used as a two-inputs logic device to simplify the architecture of the circuit. The technology used for design and simulation is SMIC 0.18 μm RF. Simulation results show that the circuit functions well under different process corners with different power supply rise time, and is able to generate a POR signal after the power supply is briefly powered off. The static power consumption is less than 30 pA. Moreover, the circuit operates properly along with other modules of analog front-end.

In the process of producing a white light emitting diode, the consistency of the optical coherence and stability of the photochromic properties is a crucial index for measuring the quality of the product. Phosphor sedimentation is a significant factor affecting optical coherence, thus, in this paper, seven sets of control experiments were set up with the phenomenon of the phosphor precipitation at time intervals 0, 2, 5, 10, 20, 30, and 40 min. The color coordination concentration and optical properties were also tested. The results indicate that phosphor sedimentation occurs between 0 and 20 min, during which the color coordinate placement is concentrated, the central coordinates are (x = 0.4432 ± 0.004, y = 0.4052 ± 0.002); the quality was verified because the supply demand chain management (SDCM) was no greater than 7. Later, between 30 and 40 min, the central coordinates are (x = 0.4366 ± 0.003, y = 0.4012 ± 0.003), which had an SDCM value higher than 7, and had a more discrete color placement; it does not meet the requirements of the national standard GBT24823-2016 general lighting LED module performance.

Zinc sulphide (ZnS) thin films have grown on glass and Si substrates by reactive cathodic radio frequency (RF) sputtering. The RF power was varied in the range of 100 to 250 W, while the deposition time is set at 75 min. The optical, structural, and morphological properties of these thin films have been studied. The optical properties (mainly thickness, refractive index, absorption coefficient, and optical band gap) were investigated by optical transmittance measurements in the wavelength range of ultraviolet-visible-near infrared spectroscopy and spectroscopy infrared with Fourier transform. Fourier (FT-IR) and XRD analysis indicated that all sputtering ZnS films had a single-phase with a preferred orientation along the (111) plane of the zinc sphalerite phase (ZB). The crystallite size ranged from 11.5 to 48.5 nm with RF power getting a maximum of 200 W. UV–visible measurements exhibited that the ZnS film had more than 80% transmission in the visible wavelength region. In addition, it has been observed that the band gap energy of ZnS films is decreased slightly from 3.52 to 3.29 eV, and as the RF power is increased, the film thickness increases with the speed of deposit growth. Scanning electron microscopy observations revealed the types of smooth-surfaced films. The measurements (FT-IR) revealed at wave number 1118 and 465.02 cm⁻¹ absorption bands corresponding to the symmetrical and asymmetric vibration of the Zn-S stretching mode. X-ray reflectometry measurements of ZnS films have shown that the density of the films is (3.9 g/cm³) close to that of solid ZnS.

Based on the effective mass approximation, the Schrödinger equation and Poisson equation in GaAs/ Al_xGa_1−xAs multi-quantum wells (MQWs) are self-consistently solved to obtain the wave functions and energy levels of electrons in the conduction band for the ground first excited state by considering a lateral electric field (LEF). Then, the effects of size, ternary mixed crystal, doping concentration, and temperature on linear and nonlinear intersubband optical absorption coefficients (IOACs), and refractive index changes (RICs) due to the transition between ground states and the first excited states of electrons are discussed based on Fermi’s golden rule. The results show that, under a fixed LEF, with increase of Al composition and doping concentration, the IOACs produce a red shift. With increases of both widths of the wells and barriers IOACs appear as blue shifts and their amplitudes increase, but the barrier width change is much more important to affect nonlinear IOACs, whereas increasing the temperature results in a blue shift first and then a red shift of IOACs. When the other parameters are fixed but there is an increase in the LEF, IOACs occur with a blue shift, and the RICs have similar properties.

Over the past few years, Cu-based materials have been intensively studied focusing on their structural and thermoelectric properties. In this work, copper sulphide powders were synthesized by the sol-gel method. The chemical composition and the morphological properties of the obtained samples were analyzed by X-ray diffraction, differential thermal analysis, and scanning electron microscopy. It is shown that the decomposition from one phase to another can be obtained by annealing. The electrical resistivity and the crystallite size were found to be strongly affected by the phase transition. Thermoelectric analyses showed that the digenite phase exhibits the highest power factor at room temperature. The Seebeck coefficient of the compound Cu_1.8S shows a pronounced peak at the γ–β transition temperature. This behavior was statistically explained in terms of a dramatic increase in the disorder in the atoms-carriers ensemble.

Reliability issues of flash memory are becoming increasingly significant with the shrinking of technology nodes. Among them, erase time degradation is an issue that draws the attention of academic and industry researchers. In this paper, causes of the " erase time degradation” are exhaustively analyzed, with proposals for its improvement presented, including a low stress program/erase scheme with a staircase pulse and disturb-immune array bias condition. Implementation of the optimized circuit structure is verified in a 128 Mb SPI NOR Flash memory chip, which is fabricated on a SMIC 65 nm ETOX process platform. Testing results indicate a degradation of the sector erase time from 10.67 to 104.9 ms after 10⁵ program/erase cycles, which exhibits an improvement of approximately 100 ms over conventional schemes.

A 2nd transconductance subharmonic receiver for 245 GHz spectroscopy sensor applications has been proposed. The receiver consists of a 245 GHz on-chip folded dipole antenna, a CB (common base) LNA, a 2nd transconductance SHM (subharmonic mixer), and a 120 GHz push-push VCO with 1/64 divider. The receiver is fabricated in f_T/f_max = 300/500 GHz SiGe:C BiCMOS technology. The receiver dissipates a low power of 288 mW. Integrated with the on-chip antenna, the receiver is measured on-chip with a conversion gain of 15 dB, a bandwidth of 15 GHz, and the chip will be utilized in PCB board design for gas spectroscopy sensor application.