A bootstrapped switch employing a new clock feed-through compensation technique

Wu Xiaofeng; Liu Hongxia; Su Li; Hao Yue; Li Di; Hu Shigang

doi:10.1088/1674-4926/30/12/125007

J. Semicond. > 2009, Volume 30 > Issue 12 > 125007

SEMICONDUCTOR INTEGRATED CIRCUITS

A bootstrapped switch employing a new clock feed-through compensation technique

Wu Xiaofeng, Liu Hongxia, Su Li, Hao Yue, Li Di and Hu Shigang

+ Author Affiliations

DOI: 10.1088/1674-4926/30/12/125007

Abstract: Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.

Key words: bootstrapped switch, clock feed-through compensation, delay path match, 设计优化

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Received: 18 August 2015 Revised: 04 September 2009 Online: Published: 01 December 2009

Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.

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