In this study, the effects of post-deposition annealing conditions and Al-doping concentrations on the electrical characteristics and bias-stress stability of ZnO-based thin-film transistors (TFTs) were systematically investigated. Experimental results reveal that an optimal annealing condition of 200°C for 30 minutes effectively promotes the activation of ionic species and the passivation of detrimental defects, thereby facilitating superior device performance. At an optimized Al-doping ratio of 1:20, the AZO TFTs exhibit excellent electrical characteristics, including a field-effect mobility of 5.03 cm²–V^–1–s^–1, a positive threshold voltage of 3.47 V and a subthreshold swing of 0.29 V/dec. Compared to pure ZnO TFTs, the Al-doped devices demonstrate exceptional bias-stress stability, which can be attributed to appropriate Al doping concentration suppressing the density of trap states, including oxygen vacancies and residual carbon-oxygen related impurities.

Ultraviolet and near ultraviolet detectors based on ZnO thin films often exhibit potential in the field of optoelectronic devices. However, the persistent photoconductivity effect inside ZnO thin films often leads to slow response speeds. In this work, a sandwich structure of NiO/ZnO/SnO₂ thin film was constructed to prepare a near ultraviolet photodetector with fast response speed. Compared with the heterojunction detectors of NiO/ZnO and ZnO/SnO₂, the sandwich structure detector exhibits significantly faster response speed (20 ms/1.65 s) under a bias voltage of 0.1 V. At the same time, the obtained device also exhibited stable self-powered response characteristics. The device exhibits a photocurrent of 1.35 nA and a response time of 20/35ms under 365nm illumination at 0V bias. The maximum responsivity and detectivity are 47.98 μA/W and 4.642 × 10⁹ Jones, respectively. The performance of the device is mainly attributed to this unique sandwich structure. The NiO and SnO₂ layers avoid direct contact between the ZnO and the electrode, effectively suppressing the influence of persistent photoconductivity of ZnO film. And the stepped energy level structure makes the transport of photo generated carriers smooth. The obtained results provide new ideas and corresponding data basis for the subsequent study of high-performance ZnO based photodetectors.

Terahertz (THz) detection finds broad application in communications, imaging, astronomy, and biomedicine, imposing core requirements for broadband operation, high speed, and high sensitivity. Two-dimensional topological semimetals with superior optoelectronic properties hold significant promise for improving sensitivity, response speed, and signal-to-noise ratio. Here, a TaIrTe₄/graphene heterojunction detector based on the type-II Weyl semimetal TaIrTe₄ is constructed. Under zero external bias, the device generates a photocurrent via the photothermoelectric (PTE) effect driven jointly by an asymmetric Seebeck coefficient and a built-in temperature gradient, enabling high-performance THz detection. The device covers a broad spectral range of 0.02−0.31 THz, achieves a peak current responsivity of 1.84 A/W, a minimum noise-equivalent power (NEP) of 30 pW·Hz^–1/2, and a response time below 300 ns. It also supports heterodyne detection, sensing weak signals from a radio-frequency (RF) source with output power below –25 dBm, and exhibits a linear dynamic range exceeding 35 dB. These results underscore the importance of exploring topological semimetals for the development of broadband, high-speed, and high-sensitivity THz detectors.

Flexible, self-powered, solar-blind ultraviolet (UV) photodetectors hold substantial promise for applications in sensing and wearable optoelectronics. In conventional Ga₂O₃ based photoelectrochemical (PEC) devices, carrier leakage at the semiconductor/electrolyte interface results in severe carrier recombination, which restricts the responsivity and severely impedes the practical deployment of such photodetectors. In addition to the aforementioned constraints, conventional rigid substrates severely hinder the translation of these materials into flexible and wearable device platforms. In this study, a PEC photodetector based on an n-α-Ga₂O₃/p-CuSCN heterojunction nanoarray was fabricated on a flexible Ti substrate. Vertically aligned α-Ga₂O₃ nanorod arrays were first prepared, followed by the introduction of CuSCN with varying loadings via controlled electrodeposition time. Under zero bias and 254 nm UV illumination, the optimized device achieved a photocurrent density of 63.42 μA∙cm^-2, which is approximately 4.2 times that of the pristine α-Ga₂O₃ device. The corresponding responsivity reached 21.14 mA∙W^-1, respectively. The intrinsic α-Ga₂O₃/electrolyte junction provides the baseline zero-bias PEC response, while the α-Ga₂O₃/CuSCN heterojunction acts as an auxiliary enhancement pathway by promoting photocarrier separation and selective hole transport, which facilitates efficient spatial separation of photogenerated charge carriers. Moreover, bending tests and repeated cycling experiments demonstrated the robust mechanical stability of the device. This work underscores the considerable potential of Ga₂O₃-based PEC photodetectors for future flexible, self-powered solar-blind UV detection applications.

GaN-on-Si HEMTs used for monolithic power integration suffer from substrate-bias-induced threshold-voltage shifts and saturation-current degradation. In this work, conventional, front-side local Si removed (FSR), and dielectric-filled FSR (Filled) devices are fabricated on the same commercial GaN-on-Si platform without backside-aligned processing. Under a substrate bias of -200 V, the conventional devices show a threshold-voltage (V_th) shift of 7.34 V and an 88% saturation-current (I_sat) degradation, whereas the FSR and Filled devices show V_th shifts of 0.35 and 0.11 V with I_sat degradations of 9% and 3%, respectively. Static and dynamic substrate-bias stress measurements further indicated reduced bias sensitivity of the FSR-based structures within the tested conditions. These results are consistent with the hypothesis that interrupting the local Si conduction path beneath the active region can mitigate substrate-bias-induced degradation.

Production-compatible wafer-thickness metrology often samples fewer than ten sites per wafer, limiting process-control decisions. This work evaluates what such sparse measurements can support, when physics priors add value, and where additional measurements are needed. We combine MOCVD and MBE simulators, leakage-safe Polynomial Ridge and XGBoost predictors, and a physics-informed Kolmogorov-Arnold Network (PI-KAN) with a weak transport-diffusion residual. Eleven reconstruction methods are tested on public wafer data comprising MOVPE/AlN, hBN, and OpenMV silicon wafers. For OpenMV mean-thickness screening, Polynomial Ridge and XGBoost reach test $R^2 \geq 0.996$ with $C_{pk} \geq 2.63$; these high values largely reflect the known eight-site mean baseline, and the incremental ML improvement is 0.050–0.053 nm. On the MOVPE benchmark, Quadratic Ridge and Gaussian Process tie for the best protocol-summary score, while PI-KAN ranks lower but supplies diagnostic value: its PDE residual correlates with reconstruction error ($\rho = 0.698$, $p = 0.008$), and model-disagreement signals correlate with held-out error. The results support an offline tiered metrology strategy: classical baselines for screening, physics-regularized overlays for diagnosis, and triggered measurements for local edge or anomaly decisions.

The von Neumann architecture faces significant challenges in efficiently processing large-scale image data due to the physical separation of memory and processing units. Inspired by the integrated memory-computing functionality of biological synapses and the quantum confinement effect of silver sulfide quantum dots (Ag₂S QDs), we develop a novel synaptic thin-film transistor with a composite-channel structure. This structure incorporates Ag₂S QDs between two indium gallium zinc oxide (IGZO) layers, forming a “sandwich” configuration. This design not only preserves the excellent electrical properties of IGZO but also extends the photoresponse range from ultraviolet to near-infrared (350−950 nm) by utilizing the broadband optical absorption characteristics of Ag₂S QDs. The resulting composite-channel devices exhibit remarkable persistent photoconductivity (PPC) and satisfactory responsivity, thereby giving rise to excellent synaptic characteristics. These include paired-pulse facilitation, the transition from short-term plasticity to long-term plasticity, and associative learning demonstrated through optoelectronic synergy in a Pavlovian conditioning experiment. Furthermore, we validated the practical utility of our synaptic devices through handwritten digit recognition. The devices successfully demonstrated effective modulation of synaptic weights via light-pulse stimulation and voltage-pulse erasure, achieving a recognition accuracy of up to 90.21%. This work provides a feasible strategy for developing broadband optoelectronic synaptic devices for neuromorphic computing applications.

Recent advancements in strain engineering of Gate−All−Around (GAA) nanosheets (NSs) make the SiGe−cladded Si channel a promising architecture for sub−3 nm logic nodes. In this work, we realize the controllable fabrication of three−stacked hexagonal SiGe−cladded Si NSs via optimized epitaxial growth and selective dry etching processes. Systematic structural characterizations including SEM, TEM and EDS confirm that the epitaxially grown SiGe cladding layer possesses excellent crystallinity and forms sharp, defect−free interfaces with the Si core, which is essential for high quality carrier transport. Beyond empirical process tuning, we further elaborate the underlying mechanism of selective etching kinetics and morphological evolution, and analyze the compressive strain modulation induced by the SiGe cladding structure. This work clarifies the critical process window for scalable three−layer stacking construction, and provides fundamental insights into process optimization, structural regulation and strain engineering for high−yield integration of next−generation GAA NS devices.

This article presents the design of a Vertical GaN Trench MOSFET featuring a Double-Diffused Base (DDB-TMOS) with an in-depth analysis of its device physics. The introduction of a lightly doped p^– GaN layer, where the channel forms, helps lower the potential barrier, improving electron transport from the n⁺ source into the n-drift region. The simulation study of the DDB-TMOS achieves a substantial reduction in threshold voltage from 10 V to 2.88 V, while the maximum current density increases from 9 kA/cm² to 21 kA/cm². As a result of structural optimization, the specific ON-resistance markedly decreases from 5.15 mΩ·cm² to 1.61 mΩ·cm². Additionally, the switching behavior of the device was systematically analyzed. The reduced base doping beneath the gate oxide led to a notable decrease in the gate-source capacitance by a factor of 1.2, decreasing the turn-on switching loss from 42 µJ/cm2 to 12 µJ/cm2. Following comprehensive static and dynamic analysis, the figure of merits (FOMs) were employed to optimize the device structure. The Baliga’s figure of merit increased from 0.68 to 2.35 GW/cm², while the switching figure of merit improved from 4.49 to 16 GHz/cm². This study confirms that the optimized DDB-TMOS is highly promising for future high-power switching applications.

This work reports deep-mesa-terminated β-Ga₂O₃ junction barrier Schottky (Mesa-JBS) diodes that achieve high breakdown voltage (BV) and ultralow reverse leakage current. The proposed architecture integrates a micron-scale deep mesa termination to suppress edge-induced leakage current with a buried p-NiO heterojunction beneath the anode to electrostatically suppress Schottky barrier tunneling, thereby mitigating both edge-related and Schottky-barrier tunneling leakage pathways. Small-area devices (0.2 × 0.2 mm²) exhibit a BV of 1.96 kV with a reverse leakage current density below 10^–5 A/cm² at 1 kV. To demonstrate scalability, large-area Mesa-JBS diodes (2 × 2 mm²) were fabricated and packaged for high-current operation. These devices deliver a forward current of 3.8 A at 3 V while sustaining a BV of up to 1.2 kV, with reverse leakage currents below 20 nA (approximately 1×10^–6 A/cm²) at 1 kV. These results establish deep-mesa-terminated JBS diodes as a promising and scalable solution for high-voltage, low-loss β-Ga₂O₃ power rectifiers.

Surface passivation is critical for HgCdTe infrared detectors. CdTe films are widely used to passivate HgCdTe surfaces owing to their close lattice match. However, achieving high-quality CdTe films for passivation remains challenging. In this study, CdTe films were deposited onto p-type HgCdTe by electron beam evaporation (EBE) at varied deposition rates, and the influence of post-deposition annealing was also assessed. Film quality and interfacial properties were evaluated by scanning electron microscopy (SEM) and capacitance–voltage (C–V) measurements. Low deposition rates without annealing produced denser, smoother films, whereas higher rates followed by annealing led to rougher surfaces. Electrically, when deposited at lowest rate without annealing, the fixed charge density reaches 1.138 × 10¹¹ cm^–2, the slow interface-state density reaches 1.067 × 10¹¹ cm^–2 and the fast interface-state density reaches 2.807 × 10¹⁰ cm^–2·eV^–1. These results underscore the importance of CdTe deposition-rate control for optimizing passivation of p-type HgCdTe.

Neural networks have provided a feasible and efficient solution for accurately predicting and maximizing the performance of materials and devices. In this perspective, we highlight a neural emulator termed TEGNet, which achieves exceptional physical fidelity (>99%) and ultra-low latency (merely 0.01% of commercial solvers) while transcending the limitations of existing artificial intelligence (AI) models through a composable architecture. This is expected to provide an efficient solution for addressing the simulation failure of flexible TEGs caused by interface slip under deformation.

Analog in-memory computing (AIMC) has attracted significant attention as an energy-efficient computing paradigm for data-intensive workloads. However, its practical deployment is fundamentally limited by various non-idealities across multiple abstraction levels, which degrade computational accuracy and reliability. This paper presents a comprehensive review of non-idealities in AIMC systems from a cross-layer perspective. A common computational representation is introduced to illustrate how diverse physical non-idealities may manifest as weight perturbations, multiplicative distortions, nonlinear transfer effects, additive errors, and quantization or accumulation errors. From this perspective, we review design techniques across device, array, circuit, data-conversion, and system levels, and discuss how errors are generated, transformed, and accumulated throughout the computation flow. Furthermore, algorithm-hardware co-design strategies are discussed as an effective approach to mitigate cross-layer errors and enhance system robustness. By providing a structured overview of error generation, transformation, and propagation, this work highlights the importance of cross-layer co-design and offers insights into the design trade-offs among accuracy, efficiency, and scalability in AIMC systems.