In this paper, a compact and low-power sub-THz direct-conversion receiver with a second-harmonic-remixed LO chain is proposed. Based on a common-mode second-harmonic-enhanced network, the common-mode second-harmonic voltage at the drains of the common-source differential pair in the tripler is enhanced and mixed with the fundamental voltage at the gate to generate additional differential third-harmonic voltage. Hence, the saturation output power and efficiency of the triplers used in the LO chain have been significantly improved. The power consumption of the LO chain employed in the receiver is as low as 65 mW. Measurement results demonstrate that the receiver achieves a conversion gain of 30.5 dB and a 3-dB RF bandwidth of 34 GHz, while the in-band minimum noise figure is 9.9 dB.

In this paper, a novel gate-series-diode structure for the Schottky-type p-GaN HEMTs is proposed, and the impact of the proposed structure on gate−source voltage oscillation is investigated when the device is turned on. The proposed structure is capable of effectively mitigating the gate−source voltage overshoot problem of GaN device, and has little effect on the switching characteristics. The gate voltage oscillations can be greatly stabilized at the steady-state turn-on voltage level when the turn-on voltage is 5 V. Compared with the conventional structure, the overshoots of the proposed structure reduce by 31.4%−71.4% and 40.6%−80.4% respectively under the two pulses, as drain−source voltage rises. The proposed structure is proved to be a potential method on improving gate reliability of the most GaN power devices.

We demonstrate room-temperature pulsed lasing of two types of GaN-based surface emitting lasers (SEL) fabricated without epitaxial regrowth. We present a direct comparison between a circular grating (CGSEL) and a photonic crystal (PCSEL) design. The devices are realized by etching the photonic structures directly into the p-GaN cladding, and utilizing a patterned indium tin oxide (ITO) top contact. Both designs exhibit lasing near 438 nm under pulsed current injection. The CGSEL, incorporating a central defect, achieves a low threshold current density (<1 kA/cm²) and a small divergence angle (≈0.15°) by coupling to a bandgap defect mode. In contrast, the PCSEL shows a higher threshold current density and lases on a 1D band-edge mode, resulting in a cross-shaped far-field pattern. These results confirm the regrowth-free method as a viable route for manufacturable GaN SELs. Crucially, the comparative study identifies the CGSEL defect-mode design as a more robust path toward high-performance lasing in low-confinement epitaxial structures.

LiNi_0.9Mn_0.1O₂ (LNM91) is a promising cobalt-free, high-energy cathode material for next-generation lithium-ion batteries, but its commercialization is challenged by rapid capacity fading resulting from bulk and interfacial structural degradation. Herein, an in situ surface-to-bulk dual-modification strategy is developed to synthesize 6Al-LNM91 (6 mol% Al modified LNM91) via a one-step calcination process based on Al diffusion chemistry. This method concurrently constructs a protective LiAlO₂ coating and incorporates Al³⁺ into the bulk lattice, effectively enhancing the structural integrity of the cathode during cycling. The optimized 6Al-LNM91 cathode delivers a remarkable rate capability of 165 mA∙h∙g⁻¹ at 10 C and maintains 94.03% capacity retention after 120 cycles at 0.5 C (2.8 − 4.4 V), substantially outperforming the pristine material (76.82% of LNM91). This organic solvent-free, single-step modification approach offers a scalable and efficient route for improving high-nickel layered oxide cathodes.

In this letter we report the morphological, electrical and thermal transport properties of a high electron mobility transistor (HEMT) style epitaxial wafer, where an approximately 2000 nm thick GaN layer has been directly deposited on a bulk single crystal AlN (BCS AlN) substrate with no buffer layer in between, and also the experimental results of DC and RF properties of a HEMT device based on such a wafer. The sample achieved very smooth surface morphology and roughness down to Ra = 0.172 nm over an area of 1 μm × 1 μm in AFM measurements. Electrical transport measurements showed sheet carrier concentration of 7.3 × 10¹² cm⁻², Hall mobility of 2220 cm²/(V·s) and sheet resistance of 386 Ω/sq. The measured maximum trans-conductance G_m of the fabricated HEMT device was 250 mS/mm at a gate bias voltage of −1.8 V. With a gate length of 500 nm and a gate-to-drain distance of 4.7 μm, the f_T and f_max, derived from S-parameters measurements, are 25.9 and 54 GHz, respectively. Large-signal RF measurement exhibited a high linear power gain (G_p) of 25.2 dB and a peak output power (P_out) density of 7.2 W/mm@1.5 GHz, associated with a power-added efficiency (PAE) of 40.9%. Comparing with the structure with a 500 nm thick AlGaN buffer, the total thermal resistance of the structure in our device decreased by 44%. This work confirms the technical feasibility of fabricating GaN HEMT devices on BCS AlN substrates without any additional buffer layer, and the excellent electric and thermal transport properties of the simplified wafer structure indicate a bright future of BCS AlN-based GaN HEMT devices in ultra-high-frequency and high-power-density nitride electronics.

In recent years, position-sensitive detectors (PSDs) have found widespread application in displacement measurement, optical measurement, imaging, and laser communication, owing to their high spatial resolution and rapid response capabilities. However, the performance and operating mechanisms of perovskite-based PSDs remain insufficiently elucidated. In this work, we fabricated a high-sensitivity self-powered PSD based on a ZnO/P(VDF-TrFE)−CH₃NH₃PbI₃(MAPbI₃) heterojunction. Systematic optimization revealed an optimal P(VDF-TrFE) doping concentration of 5 mg/mL, enabling the device to achieve a remarkable positional sensitivity (PS) of 307.03 mV/mm with a minimum nonlinearity of 1.02%. Furthermore, the intrinsic pyroelectric property of P(VDF-TrFE) induces a significant pyroelectrically enhanced lateral photovoltaic effect (LPE), boosting the PS to 511.33 mV/mm—an enhancement of 166.5%. The heterojunction PSD maintains effective operational performance over an electrode spacing range of 0.5−2.2 mm. While the LPE response declines with increasing spacing, a considerable pyroelectric effect (PE)-enhanced PS of 70.67 mV/mm is retained even at 2.2 mm. Importantly, we demonstrate multi-wavelength imaging by exploiting both the inherent LPE response and its pyroelectrically enhanced counterpart, with imaging intensity tunable via electrode spacing control. This study provides crucial insights into the LPE behavior of the heterojunction and systematically clarifies the mechanism by which the PE modulates device performance and imaging capabilities.

To address the demand for sub-100-nm overlay accuracy in wafer bonding for 3D integration, this study proposes an extended overlay assessment model integrating physical mechanisms and data-driven approaches, along with a correlation analysis methodology with process parameters. Rigid-body models inadequately characterize systematic deformations from crystalline anisotropy and process stresses. To overcome this, we construct an extended overlay model based on Zernike polynomials, incorporating physically meaningful terms for precise description of non-uniform wafer deformation. An innovative Zernike term selection strategy combining physics-guided pre-screening and AIC-optimized stepwise regression resolves overfitting/underfitting, enhancing generalizability and interpretability. Validation using Patterned Wafer Geometry (PWG) data shows the model achieves R² > 0.70 for both net bonding deformation and lithography-compensable components, demonstrating excellent deformation decomposition. Correlation analysis of multiple process experiments reveals strong correlations (|r| > 0.85) between key process parameters (e.g., peak bonding head force) and specific Zernike modes, providing evidence for suppressing detrimental deformations via process optimization. This research establishes a complete framework from theory to experimental verification and process traceability, laying a foundation for mechanism diagnosis, predictive compensation, and closed-loop control in high-precision wafer bonding.

Bulk single-crystal aluminum nitride (BSC AlN) substrates are known to be ideal platforms for constructing high-power and DUV optoelectronic nitride devices. However, high-quality epitaxial growth of nitride films on BSC AlN and related characterization is still far from being well studied. The challenges and uncertainties in doing accurate thermal characterization on such heterostructures are not fully recognized. In this study, we successfully fabricated a buffer-free thin GaN/AlN heterostructure on a BSC AlN substrate via metal−organic chemical vapor deposition (MOCVD) technology. This heterostructure consists of a 140 nm-thick AlN homoepitaxial layer and a 480 nm-thick GaN epitaxial layer. Characterization results indicate that the prepared heterojunction has excellent crystal quality and smooth surface morphology. To accurately obtain the thermophysical parameters of the heterostructure, this study employed broadband frequency domain thermoreflectance (BB-FDTR) technology, and careful measurements with detailed data analysis were demonstrated. In addition to showing the feasibility of epitaxial growth of high-quality thin film GaN directly on BSC AlN substrates, this study also provides key experimental data for evaluating the heat dissipation advantages of GaN/AlN heterostructures.

Temperature dependent photoluminescence (PL) and time-resolved PL (TRPL) of CsPbBr₃ quantum dots (QDs) in solution and film are investigated. The electron−phonon coupling strength of quantum dots in solution is found two times larger than that of thin films. The averaged phonon energy involved in luminescence is also significantly higher than that of thin films, indicating that ligands’ phonons are involved in optical processes in solution but not in film. TRPL shows that the luminescence lifetime of the solution (22.5 ns) is longer than that of the thin film (5 ns) at room temperature, and both decrease abnormally with decreasing temperature, ascribing to the thermally activated trap states for PL, the further analysis shows that the trap energy levels in the thin film are deeper (~20 meV) compared to ~4 meV in solution. Our work proves that the morphology of organic ligands can regulate electron−phonon interactions and optoelectronic properties in CsPbBr₃ QDs, providing fundamental insights into its photophysics.

This work focuses on the early-life drift mechanisms in 150 nm AlGaN/GaN HEMTs on SiC under RF-HTOL stress at 9 GHz and 130 °C. Electrical measurements during the first hours of stress reveal significant shifts in threshold voltage, transconductance, and drain lag, indicating the activation of deep traps located in the buffer. A transient increase in gate leakage current is also observed under reverse gate bias, suggesting additional trapping or conduction paths at the AlGaN/SiN or cap/passivation interface. These electrical instabilities coincide with a progressive degradation of RF performance, notably in gain and power-added efficiency. Electroluminescence measurements further support the presence of electrically active defects, with distinct spatial patterns depending on the bias configuration.

Resistive random access memories (RRAMs) are emerging as a key enabling technology for cost-effective, energy-efficient and secure chips, especially in the framework of edge computing. In particular, their electrically programmable resistance has been widely exploited in several in-memory computing and neuromorphic architectures. By adjusting the applied voltages and compliance currents (I_C), RRAM devices can be programmed to multiple resistance states during set and reset procedures, enabling multilevel functionality. While the multilevel behavior of the reset phase is generally well captured by existing compact models, only a few account for the multilevel characteristics of the set operations. Moreover, such models are rarely validated against comprehensive experimental datasets capturing device dynamics across multiple timescales. In this work, we present a physics-based compact model that enhances the UniMORE RRAM framework by incorporating the dynamic lateral evolution of the conductive filament (CF), thereby enabling accurate simulation of set operations at varying I_C values. The model is calibrated to experimental data from IHP 130 nm 1T1R RRAM technology and reproduces device behavior across several operating conditions using a single set of parameters. The results highlight the potential of the proposed compact model in design optimization workflows of RRAM-based circuits.

Fluorescence temperature sensing technology has become a research direction in the field of temperature measurement with its significant advantages of non-contact measurement, high spatial resolution, fast response and anti-electromagnetic interference. Although the double rare earth ion doping ratio fluorescent temperature sensing materials have made significant progress, the thermal quenching phenomenon is still the key bottleneck restricting its performance improvement. In this study, we propose to construct a flexible Sc₂Mo₃O₁₂:Eu³⁺/Tb³⁺ film with negative thermal expansion characteristics, and systematically study its visual temperature sensing characteristics. The negative thermal expansion characteristics of Sc₂Mo₃O₁₂ matrix effectively inhibited the thermal quenching rate of Tb³⁺ luminescence, and enhanced the thermal enhanced luminescence effect of Eu³⁺. This two-way regulation mechanism improves the intensity comparison of the two light-emitting channels, and provides an innovative strategy for improving the sensitivity of temperature sensing. The flexible film based on Eu³⁺/Tb³⁺ codoped system realizes intuitive temperature perception through the significant change of fluorescent color, and can complete the temperature interpretation without complex spectral equipment. This greatly expands its application prospect in the field of rapid field detection and real-time monitoring, and shows its broad potential in the fields of wearable devices, biomedical diagnosis, and real-time monitoring of surface temperature field.

Battery-free radio systems utilizing wireless power transfer (WPT) further facilitate the miniaturization of neural implants. However, simultaneous monitoring of multiple neuronal activities is required to obtain high-fidelity neural signals. Consequently, the integration of numerous channels on a single chip and the wireless transmission of massive multi-channel data pose significant challenges for implantable battery-free neural interfaces. This work introduces dual overlapped on-chip antennas to eliminate the need for a battery in the neural implants and enable high-data-rate backscatter for transmitting the massive data acquired simultaneously from 72 channels. Additionally, an orthogonal coding and sampling technique is employed to reduce both power consumption and area per channel. Fabricated in a 65 nm CMOS process, the proposed chip integrates 72 neural recording channels within a 2 mm × 2 mm area and achieves a backscatter data rate of 18 Mbps.

High performance flexible pressure sensors, as a very important group of electronic component for information transmission and collection, have gained widespread attention. Herein, Ti₂CT_x MXene nanosheets were vertically grown on carbon cloth substrate (Ti₂CT_x@CC) via the simple sintering and subsequent etching process. Flexible pressure sensors featuring the Ti₂CT_x MXene nanosheets as the sensitive material were then fabricated using polyvinylidene fluoride (PVDF) film weaved by the electrospinning route between the sensitive material and the interdigital electrodes to improve the sensitivity. As-fabricated flexible sensor exhibited superior performances including high sensitivity up to 3109.2 kPa⁻¹, good response and recovery time of 80/80 ms, and favorable stability over 8000 loading/unloading cycles. Boasting the high sensitivity across a broad range, the sensor can in real-time capture a spectrum of human activities—from the faint pulse signal to the large pressure of joint activities and shows promising capability for mapping spatial pressure distribution.

In fractional-N phase-locked loops, minimizing the integral nonlinearity (INL) of the digital-to-time converter (DTC) is crucial since it directly limits PLL performance. Considering the trade-off between DTC delay range and linearity, this paper presents a fractional-N dual-path SPD/PFD PLL (DP-SPFDPLL) with a complementary DTC pair. Controlled by the complementary control words, two DTCs are introduced before the two inputs of the phase detector for DTC range reduction and INL cancellation. The required DTC range is further halved by using differential VCO outputs to retime the frequency divider output. The overall design collectively achieves a 4× reduction in DTC range requirement. Fabricated in 7 nm FinFET, the DP-SPFDPLL achieves 118 fs RMS jitter and −247.5 dB figure-of-merit.

To improve the breakdown voltage (BV)−specific on-resistance (R_on,sp) trade-off and enhance manufacturability, this article proposes a novel lateral diffused metal−oxide−semiconductor (LDMOS) structure that features a split gate and split contact field plate (CFP). This novel structure requires no additional bias voltages, masks, or process steps, making it fully compatible with the bipolar-CMOS-DMOS (BCD) process flow. The physical mechanisms are elucidated through Technology computer-aided design (TCAD) simulations. In the on-state, the positively biased split gate forms an accumulation layer at the drift region surface, thereby reducing R_on,sp. In the off-state, both the split gate and split CFP introduce additional electric-field peaks that smooth the lateral electric field, thus preserving a high BV. Compared with the conventional CFP-LDMOS, the proposed CFP-LDMOS achieves an 8.52% reduction in R_on,sp without compromising BV, leading to an 8.07% improvement in the figure of merit (FOM). Notably, the proposed structure can be extended to LDMOS devices across different voltage levels within BCD platforms, demonstrating its broad applicability.

Thermoelectric power generation has attracted significant interest for its capability to directly convert thermal energy into electricity. Among various configurations, thin-film thermoelectric generators (TEGs) stand out due to their lightweight nature and facile integration, offering promising applications in waste heat recovery and wearable electronics. However, the performance of such devices under complex mechanical conditions, particularly under biaxial tensile strain, remains underexplored. In this work, we designed and fabricated a thin-film TEG insensitive to tensile strain and performed a parametric analysis using validated 3D numerical simulations to evaluate the effects of environmental conditions, material properties, and geometric parameters. Notably, the designed device maintained stable electrical performance under various biaxial tensile strains. Owing to its miniature and thin profile, variations in any component of the generator significantly affected its electrical performance. The results indicated that reduced thermal conductivity of the substrate and Ecoflex layer, as well as a thinner substrate, enhance the output voltage. Furthermore, longer thermoelectric legs within a certain range contributed to higher output voltage. Higher output voltage was more readily achieved when the inner radius length was close to the radius of the heat source. This work provides valuable insights for the development of high-performance compliant TEGs applicable in dynamic mechanical environments, such as complex stretching in the back and shoulder–elbow regions induced by human motion.

Broadband, low-power, and solution-processable organic photodetectors are essential for next-generation optoelectronic sensing. Two-dimensional conductive metal−organic frameworks (2D cMOFs) based on zinc tetracarboxyphenyl porphyrin (Zn-TCPP) offer strong light absorption and efficient charge transport, yet their photoresponse remains confined to the ultraviolet−visible (UV−Vis) region. To address this limitation, this study develops a solution-compatible strategy for constructing a well-defined MOF/organic semiconductor type-Ⅱ heterojunction by spin-coating a high-performance Y6 layer onto Zn-TCPP films. The resulting heterostructure provides complementary spectral absorption, promotes efficient exciton dissociation, and enables directional charge carrier transport, thereby achieving self-powered broadband photodetection spanning the ultraviolet to near-infrared (UV−NIR) range. The device demonstrates outstanding performance, including an ultra-low dark current (down to 3.40 × 10⁻¹³ A), high responsivity, and an ultrafast transient response with a rise time of 4.4 ms. This work establishes a generalizable approach for engineering high-efficiency MOF/organic semiconductor heterojunctions and offers a promising platform for low-cost, broadband, and self-powered photodetectors for biomedical and advanced sensing applications.

Enhanced low dose rate sensitivity (ELDRS) experiments were carried out on four commercial bipolar integrated circuits at dose rates ranging from 0.002 to 50 rad(Si)/s. Additionally, pre-irradiation elevated-temperature stress (PETS) experiments were conducted on the same devices at temperatures of 250 and 400 °C. The results show that for some devices, the radiation degradation when irradiated at an ultra-low dose rate of 0.002 rad(Si)/s is more than three times greater than that at a common low dose rate of 0.01 rad(Si)/s. Moreover, the maximum enhancement factor of the PETS effects reaches 20.3. It was also discovered that for devices exhibiting PETS effects, the saturation dose rate of ELDRS is less than 0.01 rad(Si)/s. A comprehensive analysis of the composition of the passivation layers indicated that the type and concentration of hydrogen bonds in these layers are the main factors contributing to the experimental outcomes.

High-temperature reverse bias (HTRB) is one of the most critical reliability for SiC MOSFET, and the termination region is widely regarded as the sensitive area under HTRB stress. Interestingly, through systematically monitoring of the degradation behavior of static electrical parameters under different voltage, this study reveals that the elevated reverse bias (ERB) stress can also induce damage in the gate oxide, which results in the hole trapping and a negative shift of the threshold voltage. Deep level transient spectroscopy (DLTS) measurements were performed and showed that the interface trap density in the gate oxide is promoted after ERB stress. Surprisingly, the reverse leakage current after ERB stress is significantly deteriorated at a gate bias of 0 V, while effectively suppressed by applying a negative gate bias (−5 V), which point to the synergistic effects of channel region on the breakdown voltage. Based on the gate oxide degradations and TCAD simulations, it is elucidated that the trapped positive interface charges in gate oxide cause band bending, leading to the formation of an electron accumulation layer in the channel region at 0 V gate bias and thus resulting in a dominant leakage path. This work reveals the impact and mechanism of the ERB stress induced gate oxide damage on the breakdown voltage and highlights the importance of gate oxide protection, which is of great significance for improving the reliability of SiC MOSFETs in elevated voltage applications.

Electrohydrodynamic (EHD) inkjet printing has emerged as a powerful micro-/nanofabrication technique for high-resolution perovskite quantum dot (PeQD) color-conversion layers, offering precise control over pixel morphology, dimensions, and composition. This review systematically examines the mechanisms of cone-jet and electrostatic-attraction modes in EHD printing, highlighting recent advances in PeQD ink design, solvent and ligand engineering, and printing parameter optimization. Perovskite precursor and colloidal inks are discussed in detail, emphasizing strategies to enhance droplet ejection stability, suppress coffee-ring effects, and achieve uniform, high-luminescence pixels. Ligand exchange, dual-ligand passivation, and core−shell or polymer encapsulation are shown to effectively mitigate ion migration, surface defects, and environmental degradation, thereby improving photoluminescence efficiency and stability. Multi-channel and multi-nozzle EHD printing systems enable dynamic halide composition control and parallel RGB pixel deposition, facilitating ultrahigh-resolution patterning down to submicron feature sizes. Finally, the review highlights future directions, including synergistic PeQD material synthesis, advanced ink formulation, scalable high-throughput printing, and integration of PeQD color-conversion pixels into full-color micro-LED displays with minimal crosstalk and robust operational stability. These developments collectively demonstrate the immense potential of EHD inkjet printing for next-generation high-performance display technologies.

AlN/GaN high-electron-mobility transistor (HEMT) equipped with ultra-thin AlN barrier epitaxial structures were grown on 6-inch and 8-inch Si-based GaN templates via plasma-assisted molecular beam epitaxy (PAMBE). The AlN barrier thickness was systematically optimized to improve the properties of two-dimensional electron gas (2DEG). Structural and electrical characterizations were performed by atomic force microscopy (AFM), transmission electron microscopy (TEM), contact and non-contact Hall measurements. At an optimal AlN barrier thickness, an extremely low sheet resistance of 159.9 Ω/□ by contact Hall and 143.8 Ω/□ by non-contact Hall was achieved on the 6-inch HEMT wafer, marking a significant improvement over state-of-the-art Si-based GaN HEMTs. The epitaxial surface exhibited excellent morphology with a root-mean-square (RMS) roughness of 0.45 nm. Moreover, cross-sectional TEM analysis of PAMBE-grown AlN/GaN HEMT revealed an atomically sharp and structurally coherent heterointerface, whch is critical for achieving high electron mobility and reduced scattering loss. In addition, the 8-inch HEMT demonstrated a sheet resistance (R_s) as low as 115 Ω/□ by non-contact Hall with a uniformity is 2.13%, outperforming competing technologies than other companies on the market.

Inorganic cesium lead iodide (CsPbI₃) perovskites are promising photovoltaic materials owing to their excellent thermal stability and optoelectronic properties. However, CsPbI₃ film fabricated via solution processing typically suffers from high defect densities and detrimental residual tensile stress due to uncontrolled crystallization and thermal expansion mismatch with the substrate, which impedes its practical application. Herein, we introduce ammonium benzenesulfonate (ABS) as a bifunctional additive to modulate crystallization, thereby passivating defects and regulating residual stress. The sulfonate group of ABS coordinates with undercoordinated Pb²⁺ ions, while its ammonium group forms hydrogen bonds with iodide ions. The molecular structure of ABS bridges adjacent [PbI₆]⁴⁻ octahedra at grain boundaries. This dual interaction effectively enhanced crystallinity, suppressed non-radiative recombination, and improved structural stability. As a result, ABS-modified CsPbI₃-based perovskite solar cells achieve an impressive power conversion efficiency (PCE) of 21.21% under standard illumination. Remarkably, they deliver a PCE of 40.85% under indoor lighting conditions. Moreover, unencapsulated devices retains 91% of their initial PCE after 800 h of storage in ambient air at a relative humidity of 5%.

The development of new n-type semiconductors is crucial for the further advancement of electronic and optoelectronic devices. Steamed buns, anciently known as "man tou", mainly made of wheat flour and are one of the staple foods for Chinese people. After being subjected to high-temperature treatment, the steamed buns transformed into carbonized steamed buns (CSB) with porous nanostructures, which exhibit a Hall mobility of up to 1.62 cm²/(V·s), far greater than C₆₀(1.5 × 10⁻³−2.5 × 10⁻² cm²/(V·s)), PCBM (2.0 × 10⁻⁷ cm²/(V·s)) and many polymer semiconductors (~10⁻⁶−10⁻² cm²/(V·s)). A CSB-based bulk heterojunction memristor with a configuration of ITO/the CSB: PVK blends/Al is successfully fabricated. The device shows outstanding history dependent memristive switching performance, with 35 distinguishable conductance states, at a small sweep voltage range of ±1 V. An achieved production yield reaches up to 89%. Upon being subjected to consecutive positive or negative voltage sweeps, the current flowing through the device can be modulated continuously. When the 15 consecutive pulse voltages (pulse amplitude: 0.1 V; pulse width:10 μs, pulse period: 20 μs) were applied to the device, the observed total power consumption was about 7.63 nJ, suggesting a potential in low-energy neuromorphic computing applications. As expected, both the CSB and PVK do not exhibit any memristive effect under the same experimental condition. Utilizing the characteristic that the device can linearly adjust the weights, a simple convolutional neural network for traffic sign recognition was successfully constructed. After 300 rounds of training, the achieved recognition accuracy rate reached 88.77%. This work not only provides a new approach for developing low-cost and readily available organic semiconductors with high Hall mobility, but also offers a new idea for the subsequent development of high-performance artificial synapses and optoelectronic devices using carbonized steamed buns.

This paper demonstrates a monolithically integrated current reference and current mirror based on p-GaN gate HEMT technology, designed for high-temperature applications. The p-GaN current reference is composed of one D-mode and two E-mode devices. The generated reference current is independent of supply voltage since the proposed circuit incorporates a bias circuit capable of providing a supply-voltage-insensitive bias voltage. Moreover, under the zero-temperature coefficient (ZTC) bias voltage condition, the variation in the generated reference current at 200 °C is reduced by 15.4%, compared to a conventional p-GaN current reference with a bias voltage of 5 V. Experimental results indicate that the generated reference current slightly reduced from 2.53 to 1.70 mA over a broad temperature range of 25−200 °C. In addition, a current mirror circuit based on p-GaN HEMT technology was designed to imitate a reference current. The influence of temperature on the output current of the current mirror is mitigated, which could be realised by biasing the gate-to-source voltage at the zero-temperature coefficient voltage. This design sustains the current mirror mismatch error with small variation across a temperature range from room temperature to 200 °C. These results indicate that the GaN current reference and current mirror under zero-temperature coefficient bias voltage can ensure stable output current across different temperatures, facilitating the application of fully GaN integrated circuits in high-temperature environments.

The downscaling of logic devices has posed numerous engineering and manufacturing challenges in copper (Cu) interconnections. The primary failure modes of Cu filling defects are narrow top openings and discontinuous Cu seeds on sidewalls. This study investigates the influence and mechanism of layout on Cu filling defects. Dense line wires with uneven local layouts are prone to defects, which is attributed to the altered distribution of additives in electrochemical plating (ECP), leading to differences in bottom-up filling behavior. It is demonstrated that large-sized metal conductor regions adjacent to dense line wires adsorb substantial amounts of suppressor, resulting in sparse current density in these areas. Given the fixed total local current density, the sparseness of current density in adjacent regions inevitably diverts more current lines to the dense line wire areas. The excessive current density exceeds the local redistribution capacity of additives, causing premature sealing of trench tops and the formation of void defects. A low-current plating process significantly mitigates these defects but may compromise the protective capability of the Cu seed. Additionally, the perimeter density of the layout serves as an effective evaluation index.

This work focuses on the study of the resistive switching (RS) properties of metal−insulator−semiconductor (MIS)-like structures based on silicon nitride (Si₃N₄) and Si₃N₄ with embedded silicon nanocrystals (Si-NCs) as the switching layer for the development of memristor devices. The formation of Si-NCs in the Si₃N₄ matrix, along with its chemical composition, was confirmed by Raman, transmission electron microscope (TEM), and energy-dispersive X-ray spectroscopy (EDS) analyses. The introduction of Si-NCs within the Si₃N₄ improved the performance of the devices. For Si₃N₄-based memristor devices, SET and RESET voltages of 2.38 and −1.38 V were obtained, respectively, while these values were reduced to 0.36 V (SET) and −0.11 V (RESET) for Si₃N₄:Si-NCs-based RS devices. Both RS devices exhibit at least 180 RS cycles, but with an increased ON/OFF ratio from 10³ (Si₃N₄) to 10⁶ when Si-NCs are embedded. The retention time analysis shows that the low resistance state (LRS) and the high resistance state (HRS) are stable for up to 10⁴ s. The analysis of the conduction mechanism indicates that HRS is driven by the space-charge-limited conduction (SCLC), and the LRS by an Ohmic conduction mechanism. A model of the RS mechanism was proposed to understand the role of Si-NCs in the dielectric matrix.

This paper demonstrated a monolithically integrated 200 nm-ultrathin amorphous-Ga₂O₃ vertical SBD-based bridge rectifier and its hybrid buck conversion system with a Si-MOSFET. The fabricated vertical Ga₂O₃ SBD exhibits excellent characteristics and a high breakdown electric field strength of 1.35 MV/cm. The bridge rectifier circuit maintains stable operation at high frequencies of 50 kHz. And the hybrid buck system composed of the Ga₂O₃ bridge rectifier and Si-MOSFET achieves adjustable step-down voltage output under the conditions of a 20 kHz switching frequency of Si-MOSFET and 50 Hz V_in. This work validates the practical value of Ga₂O₃ rectifiers in high-frequency conversion systems.

High gate oxide electric field, which can lead to device failure, is a common issue in SiC MOSFETs. To mitigate this issue and ensure high device reliability, an electric field shielding layer (also called depletion layer) in JFET region is always used to reduce the gate oxide electric filed strength (E_ox,max). However, there is still a lack of a detection methods to characterize the changes in the depletion layer of the JFET region. In this paper, a type of 1200 V 4H-SiC MOSFET with different JFET widths and cell topologies is designed and fabricated, and an innovative detection method for the depletion layer of JFET region is proposed for the first time. This method is adopted to focus on discussing the influence of the depletion layer formed by different JFET widths on V_g, and the changes in the gate oxide capacitance C_g of hexagonal cells and linear cells during the formation of the JFET depletion layer are studied. Finally, the robustness of different cell topologies and JFET widths is determined by the depletion voltage drift in the high temperature gate reverse bias tests (HTGB−) reliability test.

Spin-transfer-torque magnetic random-access memory (STT-MRAM), based on magnetic tunnel junctions (MTJs), is attracting significant attention for applications demanding high reliability and speed. To ensure high TMR which is essential for achieving sufficient sense margin, MTJs typically incorporate relatively thick tunnel barriers, resulting in high operating voltages. As the CMOS technology nodes advance and operating voltages decrease, reducing the MTJ switching voltage becomes imperative. However, MTJs with thinner tunnel barriers generally exhibit significantly degraded read margins and bit error rate, presenting a major challenge for achieving high-density, low-power MRAM. Here, we address this challenge through MgO tunnel barrier engineering and process optimization, successfully reducing the required MOS driving voltage while simultaneously expanding the write margin. Meanwhile, 85% array yield with sub-parts-per-million bit error rates at RA = 7 Ω·μm² is achieved. These advancements are promising for developing high-density MRAM at advanced technology nodes.

Chemical mechanical polishing (CMP) serves as an indispensable process for achieving global planarization in semiconductor manufacturing, especially as integrated circuit (IC) technology advances to sub-7 nm nodes, where atomic-level surface flatness becomes crucial. Silica abrasives, which account for over 90% of the abrasive market in advanced CMP processes, operate not through simple mechanical grinding but through a key "chemical-mechanical synergistic" mechanism: chemically softening the wafer surface, then mechanically removing the softened layer to expose a new surface, which is further softened and removed, repeating this cycle to produce a smooth wafer. Despite their prevalence, conventional silica abrasives still face challenges, including relatively low material removal rate (MRR), a tendency to agglomerate, leading to poor dispersion and surface defects, and limitations in achieving ultimate surface uniformity. Significant progress has been made to address these issues. Development has progressed from simple spherical particles to complex structural designs (such as mesoporous, hollow, and raspberry-shaped structures) to enhance slurry transport and mechanical action. Surface chemical modifications (e.g., using amino or polymer groups) can improve dispersion stability and reduce scratching. Furthermore, composites with other materials (e.g., ceria, polymers) and precise control of particle size distribution are key to enhancing performance. These innovative approaches have yielded significant performance gains. State-of-the-art slurries have demonstrated the ability to achieve surface roughness below 0.1 nm rms. The development of silica abrasives is increasingly focused on sustainability and smart manufacturing. A prominent direction is the design of biodegradable abrasives that disintegrate after use, thereby simplifying post-chemical mechanical polishing (CMP) cleanup and minimizing environmental impact—an approach fully aligned with green manufacturing principles. This review systematically summarizes the progress of silica abrasives for CMP over the past 60 years. This summary provides theoretical insights and forward-looking strategies to overcome the current limitations of abrasive technology. We believe this review will be helpful in advancing the field of CMP abrasives towards next-generation semiconductor manufacturing.

In this work, the oxide-based programmable diodes (PDs) with structure of TiN/HfO₂/Si/Al are fabricated, and its electron transport mechanisms are investigated. Electrical measurements results depicted that the conduction and rectification performance of oxide-based PDs are mainly controlled by the interface between oxygen vacancies (VOs) consisted filament and semiconductor electrode. The local density of state in filament and band-bending of the PDs are calculated by first-principal simulation. The electron transport in oxide PDs is dominated by Poole−Frenkel emission under forward bias, while under negative bias, the PDs behave like a reverse Schottky-diode. These mechanisms research is necessary for device optimization and circuit design of oxide-based PDs.