Simulation and fabrication of vertical channel transistors with self-aligned high-κ metal gates using ion implantation for source/drain doping

Penghui Sun; Yongkui Zhang; Jun Luo

doi:10.1088/1674-4926/25030043

J. Semicond. > Just Accepted

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Simulation and fabrication of vertical channel transistors with self-aligned high-κ metal gates using ion implantation for source/drain doping

Penghui Sun^{1, 2}, Yongkui Zhang^2, and Jun Luo^{1, 2,}

+ Author Affiliations

Corresponding author: Yongkui Zhang, zhangyongkui@ime.ac.cn; Jun Luo, luojun@ime.ac.cn

DOI: 10.1088/1674-4926/25030043CSTR: 32376.14.1674-4926.25030043

Abstract: In vertical channel transistors (VCTs), source/drain ion implantation (I/I) represents a significant technical challenge due to inherent three-dimensional structural constraints, which induce complications such as difficulties in dummy gate formation and shadowing effects of I/I. This article systematically investigates the impact of different implantation conditions on the performance of VCTs with and without dummy gates through TCAD simulation. It reveals the significant role of the lightly doped regions (LDRs) naturally formed due to ion implantation in source/drain of VCTs. Furthermore, it was found that VCT without dummy gates can achieve an approximately 27% increase in on-state current (I_on) under the same implantation conditions, and can greatly simplify the process flow and reduce costs. Finally, N-type and P-type VCTs were successfully fabricated using this implantation method.

Key words: vertical channel transistor, source/drain ion implantation, on-state current, dummy gates

References

[1]	Takato H, Sunouchi K, Okabe N, et al. Impact of surrounding gate transistor (SGT) for ultra-high-density LSI’s. IEEE Trans Electron Devices, 1991, 38(3), 573 doi: 10.1109/16.75168
[2]	Jagannathan H, Anderson B, Sohn C W, et al. Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices. 2021 IEEE International Electron Devices Meeting (IEDM), 2021, 26.1.1
[3]	Thean A V, Yakimets D, Huynh Bao T, et al. Vertical device architecture for 5nm and beyond: device & circuit implications. 2015 Symposium on VLSI Technology (VLSI Technology), 2015, T26
[4]	Yakimets D, Eneman G, Schuddinck P, et al. Vertical GAAFETs for the ultimate CMOS scaling. IEEE Trans Electron Devices, 2015, 62(5), 1433 doi: 10.1109/TED.2015.2414924
[5]	Yakimets D, Huynh Bao T, Bardon M G, et al. Lateral versus vertical gate-all-around FETs for beyond 7nm technologies. 72nd Device Research Conference, 2014, 133
[6]	Song T. Opportunities and challenges in designing and utilizing vertical nanowire FET (V-NWFET) standard cells for beyond 5 nm. IEEE Trans Nanotechnol, 2019, 18, 240 doi: 10.1109/TNANO.2019.2896362
[7]	Veloso A, Huynh-Bao T, Rosseel E, et al. Challenges and opportunities of vertical FET devices using 3D circuit design layouts. 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016, 1
[8]	Veloso A, Altamirano-Sánchez E, Brus S, et al. (invited) vertical nanowire FET integration and device aspects. ECS Trans, 2016, 72(4), 31 doi: 10.1149/07204.0031ecst
[9]	Veloso A, Eneman G, Huynh-Bao T, et al. Vertical nanowire and nanosheet FETs: device features, novel schemes for improved process control and enhanced mobility, potential for faster & more energy efficient circuits. 2019 IEEE International Electron Devices Meeting (IEDM), 2019, 11.1.1
[10]	Yin X G, Zhang Y K, Zhu H L, et al. Vertical sandwich gate-all-around field-effect transistors with self-aligned high-k metal gates and small effective-gate-length variation. IEEE Electron Device Lett, 2020, 41(1), 8 doi: 10.1109/LED.2019.2954537
[11]	Zhang Y K, Ai X Z, Yin X G, et al. Vertical sandwich GAA FETs with self-aligned high-k metal gate made by quasi atomic layer etching process. IEEE Trans Electron Devices, 2021, 68(6), 2604 doi: 10.1109/TED.2021.3072879
[12]	Xiao Z R, Wang Q, Zhu H L, et al. Vertical C-shaped-channel nanosheet FETs featured with precise control of both channel-thickness and gate-length. IEEE Electron Device Lett, 2022, 43(8), 1183 doi: 10.1109/LED.2022.3187006
[13]	Li J J, Li Y L, Zhou N, et al. Study of silicon nitride inner spacer formation in process of gate-all-around nano-transistors. Nanomaterials, 2020, 10(4), 793 doi: 10.3390/nano10040793
[14]	Li C, Zhu H L, Zhang Y K, et al. First demonstration of novel vertical gate-all-around field-effect-transistors featured by self-aligned and replaced high-κ metal gates. Nano Lett, 2021, 21(11), 4730 doi: 10.1021/acs.nanolett.1c01033
[15]	Gnani E, Gnudi A, Reggiani S, et al. Theory of the junctionless nanowire FET. IEEE Trans Electron Devices, 2011, 58(9), 2903 doi: 10.1109/TED.2011.2159608
[16]	Ogura S, Tsang P J, Walker W W, et al. Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor. IEEE J Solid State Circuits, 1980, 15(4), 424 doi: 10.1109/JSSC.1980.1051416

Fig. 1. (Color online) (a) VCT with dummy gates before ion implantation. (b) VCT without dummy gates before ion implantation. (c) The final device structure. (d) Comparison of I_d−V_g curves between simulation (sim.) and experiment (exp.).

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) Process flow for fabricating n-type and p-type VCTs without dummy gates.

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) Electrical properties of VCT with dummy gates at various ion implantation conditions. (a) I_d−V_g curves. (b) I_on (c) I_on/I_off (d) I_off (e) SS (f) DIBL.

DownLoad: Full-Size Img PowerPoint

Fig. 4. (Color online) Doping profiles of VCT with dummy gates at different tilt angles and implantation energies.

DownLoad: Full-Size Img PowerPoint

Fig. 5. (Color online) Electrical properties of VCT without dummy gates at various ion implantation conditions. (a) I_d−V_g curves. (b) I_on (c) I_on/I_off (d) I_off (e) SS (f) DIBL.

DownLoad: Full-Size Img PowerPoint

Fig. 6. (Color online) Doping profiles of VCT without dummy gates at different implantation energies and tilt angles.

DownLoad: Full-Size Img PowerPoint

Fig. 7. (Color online) The comparison of I_on between VCTs with dummy gates (w.DG) and without dummy gates (w.o.DG) at various ion implantation conditions.

DownLoad: Full-Size Img PowerPoint

Fig. 8. (Color online) Doping profiles of VCT w.DG and w.o.DG at various tilt angles when the implantation energy is 40 keV.

DownLoad: Full-Size Img PowerPoint

Fig. 9. (Color online) The key steps in the fabrication of VCT without dummy gates. (a) Selective etch SiGe to form gate gap. (b) Epitaxial growth Si channel. (c) Inside of nanosheet fabrication by spacer image transfer. (d) SiGe and oxide release.

DownLoad: Full-Size Img PowerPoint

Fig. 10. (Color online) (a) I_d−V_g curves of n-type VCT. (b) I_d−V_d curves of n-type VCT. (c) I_d−V_g curves of p-type VCT. (c) I_d−V_g curves of p-type VCT.

DownLoad: Full-Size Img PowerPoint

Fig. 11. (Color online) The V−I curves of NMOS and PMOS obtained using the kelvin method.

DownLoad: Full-Size Img PowerPoint

Fig. 12. The contact resistance test curves of NMOS and PMOS

DownLoad: Full-Size Img PowerPoint

Table 1. Device parameter settings in the simulation.

Device Parameters	Value
Lch /nm	60
Wch /nm	20
Wsd /nm	100
Hsd /nm	100
EOT /nm	1.6

DownLoad: CSV

[1]	Takato H, Sunouchi K, Okabe N, et al. Impact of surrounding gate transistor (SGT) for ultra-high-density LSI’s. IEEE Trans Electron Devices, 1991, 38(3), 573 doi: 10.1109/16.75168
[2]	Jagannathan H, Anderson B, Sohn C W, et al. Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices. 2021 IEEE International Electron Devices Meeting (IEDM), 2021, 26.1.1
[3]	Thean A V, Yakimets D, Huynh Bao T, et al. Vertical device architecture for 5nm and beyond: device & circuit implications. 2015 Symposium on VLSI Technology (VLSI Technology), 2015, T26
[4]	Yakimets D, Eneman G, Schuddinck P, et al. Vertical GAAFETs for the ultimate CMOS scaling. IEEE Trans Electron Devices, 2015, 62(5), 1433 doi: 10.1109/TED.2015.2414924
[5]	Yakimets D, Huynh Bao T, Bardon M G, et al. Lateral versus vertical gate-all-around FETs for beyond 7nm technologies. 72nd Device Research Conference, 2014, 133
[6]	Song T. Opportunities and challenges in designing and utilizing vertical nanowire FET (V-NWFET) standard cells for beyond 5 nm. IEEE Trans Nanotechnol, 2019, 18, 240 doi: 10.1109/TNANO.2019.2896362
[7]	Veloso A, Huynh-Bao T, Rosseel E, et al. Challenges and opportunities of vertical FET devices using 3D circuit design layouts. 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016, 1
[8]	Veloso A, Altamirano-Sánchez E, Brus S, et al. (invited) vertical nanowire FET integration and device aspects. ECS Trans, 2016, 72(4), 31 doi: 10.1149/07204.0031ecst
[9]	Veloso A, Eneman G, Huynh-Bao T, et al. Vertical nanowire and nanosheet FETs: device features, novel schemes for improved process control and enhanced mobility, potential for faster & more energy efficient circuits. 2019 IEEE International Electron Devices Meeting (IEDM), 2019, 11.1.1
[10]	Yin X G, Zhang Y K, Zhu H L, et al. Vertical sandwich gate-all-around field-effect transistors with self-aligned high-k metal gates and small effective-gate-length variation. IEEE Electron Device Lett, 2020, 41(1), 8 doi: 10.1109/LED.2019.2954537
[11]	Zhang Y K, Ai X Z, Yin X G, et al. Vertical sandwich GAA FETs with self-aligned high-k metal gate made by quasi atomic layer etching process. IEEE Trans Electron Devices, 2021, 68(6), 2604 doi: 10.1109/TED.2021.3072879
[12]	Xiao Z R, Wang Q, Zhu H L, et al. Vertical C-shaped-channel nanosheet FETs featured with precise control of both channel-thickness and gate-length. IEEE Electron Device Lett, 2022, 43(8), 1183 doi: 10.1109/LED.2022.3187006
[13]	Li J J, Li Y L, Zhou N, et al. Study of silicon nitride inner spacer formation in process of gate-all-around nano-transistors. Nanomaterials, 2020, 10(4), 793 doi: 10.3390/nano10040793
[14]	Li C, Zhu H L, Zhang Y K, et al. First demonstration of novel vertical gate-all-around field-effect-transistors featured by self-aligned and replaced high-κ metal gates. Nano Lett, 2021, 21(11), 4730 doi: 10.1021/acs.nanolett.1c01033
[15]	Gnani E, Gnudi A, Reggiani S, et al. Theory of the junctionless nanowire FET. IEEE Trans Electron Devices, 2011, 58(9), 2903 doi: 10.1109/TED.2011.2159608
[16]	Ogura S, Tsang P J, Walker W W, et al. Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor. IEEE J Solid State Circuits, 1980, 15(4), 424 doi: 10.1109/JSSC.1980.1051416

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Received: 27 March 2025 Revised: 27 May 2025 Online: Accepted Manuscript: 17 June 2025

Article Navigation > Journal of Semiconductors > 2025 > Accepted Manuscript

Penghui Sun, Yongkui Zhang, Jun Luo. Simulation and fabrication of vertical channel transistors with self-aligned high-κ metal gates using ion implantation for source/drain doping[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/25030043 ****P H Sun, Y K Zhang, and J Luo, Simulation and fabrication of vertical channel transistors with self-aligned high-κ metal gates using ion implantation for source/drain doping[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/25030043

Citation:

P H Sun, Y K Zhang, and J Luo, Simulation and fabrication of vertical channel transistors with self-aligned high-κ metal gates using ion implantation for source/drain doping[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/25030043

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Simulation and fabrication of vertical channel transistors with self-aligned high-κ metal gates using ion implantation for source/drain doping

DOI: 10.1088/1674-4926/25030043

CSTR: 32376.14.1674-4926.25030043

Penghui Sun^{1, 2},
Yongkui Zhang^2,,
Jun Luo^{1, 2,}

1.
University of Chinese Academy of Sciences, School of integrated circuits, Beijing 100049, China
2.
Integrated Circuit Advanced Process R & D Center, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

More Information

Penghui Sun got his BS degree from Central South University of Forestry and Technology in 2022. Now he is MS student in University of Chinese Academy of Sciences under the supervision of Yongkui Zhang engineer. His research focus on advance CMOS technology
Yongkui Zhang obtained his M.s degree in 2004 in Beijing University of science and technology. He worked at Semiconductor Manufacturing International Corporation in 2004−2012. He joined the institute of Microelectronics of Chinese Academy of Sciences in 2012. His research interests are mainly focused on advanced CMOS technology research
Corresponding author: zhangyongkui@ime.ac.cn; luojun@ime.ac.cn
Received Date: 2025-03-27
Revised Date: 2025-05-27

Available Online: 2025-06-17

Abstract

Abstract

In vertical channel transistors (VCTs), source/drain ion implantation (I/I) represents a significant technical challenge due to inherent three-dimensional structural constraints, which induce complications such as difficulties in dummy gate formation and shadowing effects of I/I. This article systematically investigates the impact of different implantation conditions on the performance of VCTs with and without dummy gates through TCAD simulation. It reveals the significant role of the lightly doped regions (LDRs) naturally formed due to ion implantation in source/drain of VCTs. Furthermore, it was found that VCT without dummy gates can achieve an approximately 27% increase in on-state current (I_on) under the same implantation conditions, and can greatly simplify the process flow and reduce costs. Finally, N-type and P-type VCTs were successfully fabricated using this implantation method.
- vertical channel transistor,
- source/drain ion implantation,
- on-state current,
- dummy gates

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References(16)