Dynamic avalanche reliability enhancement of FS-IGBT under unclamped inductive switching

Jingping Zhang; Houcai Luo; Huan Wu; Bofeng Zheng; Xianping Chen

doi:10.1088/1674-4926/25020006

J. Semicond. > Just Accepted

ARTICLES

Dynamic avalanche reliability enhancement of FS-IGBT under unclamped inductive switching

Jingping Zhang¹, Houcai Luo¹, Huan Wu¹, Bofeng Zheng¹ and Xianping Chen^{1, 2,}

+ Author Affiliations

Corresponding author: Xianping Chen, xianpingchen@cqu.edu.cn

DOI: 10.1088/1674-4926/25020006CSTR: 32376.14.1674-4926.25020006

Abstract: The dynamic avalanche effect is a critical factor influencing the performance and reliability of the field-stop insulated gate bipolar transistors (FS-IGBT). Unclamped inductive switching (UIS) is the primary method for testing the dynamic avalanche capability of FS-IGBTs. Numerous studies have demonstrated that factors such as device structure, avalanche-generating current filaments, and electrical parameters influence the dynamic avalanche effect of the FS-IGBT. However, few studies have focused on enhancing the avalanche reliability of the FS-IGBT by adjusting circuit parameters during operation. In this paper, the dynamic avalanche effect of the FS-IGBT under UIS conditions is comprehensively investigated through a series of comparative experiments with varying circuit parameters, including bus voltage V_DC, gate voltage V_G, gate resistance R_g, load inductance L, and temperature T_C. Furthermore, a method to enhance the dynamic avalanche reliability of the FS-IGBT under UIS by optimizing circuit parameters is proposed. In practical applications, reducing gate voltage, increasing load inductance, and lowering temperature can effectively improve the dynamic avalanche capability of the FS-IGBT.

Key words: FS-IGBT, dynamic avalanche, UIS, reliability, circuit parameters.

References

[1]	Breglio G, Irace A, Napoli E, et al. Study of a failure mechanism during UIS switching of planar PT-IGBT with current sense cell. Microelectron Reliab, 2007, 47(9/10/11), 1756
[2]	Liu S Y, Tong X, Wei J X, et al. Single-pulse avalanche failure investigations of Si-SJ-mosfet and SiC-mosfet by step-control infrared thermography method. IEEE Trans Power Electron, 2020, 35(5), 5180 doi: 10.1109/TPEL.2019.2946792
[3]	Hasegawa K, Taguchi K, Kagawa Y, et al. Which is harder SOA test for SiC MOSFET to do Unclamped Inductive Switching (UIS) or Unloaded Short Circuit mode Switching (USCS)? Does UIS play a role of USCS? 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2020, 62
[4]	Z H, Lin Z, Hu S D, et al. Comparative study on the short-circuit withstand capability between the superjunction and conventional field-stop IGBTs. Microelectron Reliab, 2024, 156, 115387 doi: 10.1016/j.microrel.2024.115387
[5]	Sano K, Matsushita Y, Yachi M, et al. Small current unclamped inductive switching (UIS) to detect fabrication defect for mass-production phase IGBT. 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018, 116
[6]	Ren N, Wang K L, Wu J P, et al. Failure mechanism analysis of SiC MOSFETs in unclamped inductive switching conditions. 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2019, 183
[7]	Ma X, Huang Y L, Tang X, et al. Numerical modeling of FS-trench IGBTs by TCAD and its parameter extraction method. Microelectron Reliab, 2023, 147, 115053 doi: 10.1016/j.microrel.2023.115053
[8]	Tanaka M, Nakagawa A. Simulation studies for avalanche induced short-circuit current crowding of MOSFET-Mode IGBT. 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC’s (ISPSD), 2015, 121
[9]	Endo K, Nagamine S, Saito W, et al. Direct photo emission motion observation of current filaments in the IGBT under avalanche breakdown condition. 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2016, 367
[10]	Li L P, Li Z H, Wu Y Z, et al. Investigation on robust avalanche capacity of super-junction IGBT under UIS stress. IEEE Trans Electron Devices, 2024, 71(8), 4853 doi: 10.1109/TED.2024.3408774
[11]	Riccio M, Irace A, Breglio G, et al. Electro-thermal instability in multi-cellular Trench-IGBTs in avalanche condition: Experiments and simulations. 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, 2011, 124
[12]	Suzuki H, Ciappa M. TCAD simulation of current filamentation in adjacent IGBT cells under turn-on and turn-off short circuit condition. Microelectron Reliab, 2015, 55(9/10), 1976
[13]	Shankar B, Zeng K, Gunning B, et al. Movement of current filaments and its impact on avalanche robustness in vertical GaN P-N diode under UIS stress. 2022 Device Research Conference (DRC), 2022, 1
[14]	Endo K, Chinone N, Nakamura T, et al. Single-pulse observation of photoemission during avalanche breakdown in insulated gate bipolar transistor. Microelectron Reliab, 2020, 114, 113739 doi: 10.1016/j.microrel.2020.113739
[15]	Breglio G, Irace A, Napoli E, et al. Detection of localized UIS failure on IGBTs with the aid of lock-in thermography. Microelectron Reliab, 2008, 48(8/9), 1432
[16]	Suwa T. 2D-TCAD simulation study of capture layer and repellent layer of current filament in trench-gate IGBTs. 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, 32
[17]	Breglio G, Irace A, Napoli E, et al. Experimental detection and numerical validation of different failure mechanisms in IGBTs during unclamped inductive switching. IEEE Trans Electron Devices, 2013, 60(2), 563 doi: 10.1109/TED.2012.2226177
[18]	Shoji T, Ishiko M, Fukami T, et al. Investigations on current filamentation of IGBTs under undamped inductive switching conditions. Proceedings of ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005, 227
[19]	Tanaka M, Abe N, Nakagawa A. Impact of 3D simulation on the analysis of unclamped inductive switching. Jpn J Appl Phys, 2020, 59, SGGD01
[20]	Spirito P, Breglio G, Irace A, et al. Physics of the negative resistance in the avalanche $I {-} V$ curve of field stop IGBTs: Collector design rules for improved ruggedness. IEEE Trans Electron Devices, 2014, 61(5), 1457 doi: 10.1109/TED.2014.2311169
[21]	Spirito P, Maresca L, Riccio M, et al. Effect of the collector design on the IGBT avalanche ruggedness: A comparative analysis between punch-through and field-stop devices. IEEE Trans Electron Devices, 2015, 62(8), 2535 doi: 10.1109/TED.2015.2442334
[22]	Tong X, Liu S Y, Sun W F, et al. Complete avalanche process and failure mechanism of trench-gate FS-IGBT under unclamped inductive switching by using infrared visualization method. IEEE Trans Electron Devices, 2020, 67(9), 3908 doi: 10.1109/TED.2020.3011644
[23]	Bao X K, Zhu A K, Chen R T, et al. Voltage-balanced behavioral model considering carrier extraction effect for series-connected trench gate FS-IGBTs. 2022 IEEE International Power Electronics and Application Conference and Exposition (PEAC), 2022, 566

Fig. 1. (Color online) Cross-sectional (a) cell and (b) terminal structure view of the FS-IGBT.

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Fig. 2. (Color online) Cross-sectional cell structure view of the four topologies of the FS-IGBT.

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Fig. 3. (Color online) Simulated V_CEsat and E_off as a function of cell topologies.

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Fig. 4. (Color online) Simulated (a) transfer characteristics, (b) forward conduction and (c) forward blocking of the FS-IGBT.

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Fig. 5. (Color online) The manufacturing process of the FS-IGBT. (a) CS Layer and P base, (b) trench etching, gate oxide growth, and polysilicon deposition, (c) N+ emitter region, (d) CT opening and P+ emitter region, (e) passivation layer and polyimide, (f) FS layer, P+ region and metallization.

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Fig. 6. (Color online) (a) A quarter of 12-inch wafer and (b) TO-247 packaged device of the 650V 75A FS-IGBT.

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Fig. 7. (Color online) Keysight B1506A power device analyzer for circuit design.

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Fig. 8. (Color online) Measured (a) transfer characteristics, (b) forward conduction and (c) forward blocking of the FS-IGBT.

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Fig. 9. UIS test circuit.

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Fig. 10. (Color online) UIS test waveform.

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Fig. 11. (Color online) UIS test platform.

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Fig. 12. (Color online) Measured UIS waveforms of FS-IGBT at different bus voltages V_DC for the same gate pulse.

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Fig. 13. (Color online) Measured (a) UIS waveforms, (b) t_AS and E_AS as a function of V_DC for the FS-IGBT with different gate pulses at different bus voltages V_DC.

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Fig. 14. (Color online) Measured UIS waveforms of FS-IGBT at different gate voltages V_G for the same gate pulse.

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Fig. 15. (Color online) Measured (a) UIS waveforms, (b) I_AS, t_AS and E_AS as a function of V_G for the FS-IGBT with different gate pulses at different gate voltages V_G.

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Fig. 16. (Color online) Measured UIS waveforms of FS-IGBT with different gate resistance R_g: (a) the same gate pulse t_on = 200 μs, (b) the limit gate pulse t_on = 425 μs.

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Fig. 17. (Color online) (a) Measured UIS waveforms, (b) internal lattice temperature for TCAD simulation and (c) simulated lattice temperature curves in the longitudinal direction of FS-IGBT at different load inductance L for the same gate pulse.

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Fig. 18. (Color online) Measured (a) UIS waveforms, (b) t_AS and E_AS as a function of L for the FS-IGBT with different gate pulses at different load inductance L.

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Fig. 19. (Color online) (a) Measured UIS waveforms and (b) simulated lattice temperature curves of FS-IGBT at different temperature T_C for the same gate pulse.

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Fig. 20. (Color online) Measured (a) UIS waveforms, (b) I_AS, t_AS and E_AS as a function of T_C for the FS-IGBT with different gate pulses at different temperature T_C.

DownLoad: Full-Size Img PowerPoint

Table 1. Simulation parameters of the FS-IGBT structure.

Symbol	Structure Parameter	Value	Unit
T_CP+	Collector P+ region depth	1.0	μm
N_CP+	Collector P+ doping concentration	3.0 × 10¹⁷	cm^-3
T_FS	FS layer depth	2.0	μm
N_FS	FS layer doping concentration	3.0 × 10¹⁶	cm^-3
T_d	Drift thickness	57.0	μm
N_d	Drift doping concentration	1.0 × 10¹⁴	cm^-3
T_t	Trench depth	5.0	μm
W_t	Trench width	1.0	μm
T_ox	Gate oxide thickness	0.12	μm
T_CS	Carrier storage (CS) layer depth	2.5	μm
N_CS	CS layer doping concentration	3.0 × 10¹⁵	cm^-3
T_Pbase	P base depth	3.0	μm
N_Pbase	P base doping concentration	1.0 × 10¹⁷	cm^-3
T_N+	N+ depth	0.3	μm
L_N+	N+ length	0.2	μm
N_N+	N+ doping concentration	1.0 × 10²⁰	cm^-3
T_P+	P+ depth	0.6	μm
L_P+	P+ length	0.4	μm
N_P+	P+ doping concentration	1.0 × 10²⁰	cm^-3
T_CT	Contact (CT) depth	0.4	μm
L_CT	CT length	0.3	μm

DownLoad: CSV

[1]	Breglio G, Irace A, Napoli E, et al. Study of a failure mechanism during UIS switching of planar PT-IGBT with current sense cell. Microelectron Reliab, 2007, 47(9/10/11), 1756
[2]	Liu S Y, Tong X, Wei J X, et al. Single-pulse avalanche failure investigations of Si-SJ-mosfet and SiC-mosfet by step-control infrared thermography method. IEEE Trans Power Electron, 2020, 35(5), 5180 doi: 10.1109/TPEL.2019.2946792
[3]	Hasegawa K, Taguchi K, Kagawa Y, et al. Which is harder SOA test for SiC MOSFET to do Unclamped Inductive Switching (UIS) or Unloaded Short Circuit mode Switching (USCS)? Does UIS play a role of USCS? 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2020, 62
[4]	Z H, Lin Z, Hu S D, et al. Comparative study on the short-circuit withstand capability between the superjunction and conventional field-stop IGBTs. Microelectron Reliab, 2024, 156, 115387 doi: 10.1016/j.microrel.2024.115387
[5]	Sano K, Matsushita Y, Yachi M, et al. Small current unclamped inductive switching (UIS) to detect fabrication defect for mass-production phase IGBT. 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018, 116
[6]	Ren N, Wang K L, Wu J P, et al. Failure mechanism analysis of SiC MOSFETs in unclamped inductive switching conditions. 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2019, 183
[7]	Ma X, Huang Y L, Tang X, et al. Numerical modeling of FS-trench IGBTs by TCAD and its parameter extraction method. Microelectron Reliab, 2023, 147, 115053 doi: 10.1016/j.microrel.2023.115053
[8]	Tanaka M, Nakagawa A. Simulation studies for avalanche induced short-circuit current crowding of MOSFET-Mode IGBT. 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC’s (ISPSD), 2015, 121
[9]	Endo K, Nagamine S, Saito W, et al. Direct photo emission motion observation of current filaments in the IGBT under avalanche breakdown condition. 2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2016, 367
[10]	Li L P, Li Z H, Wu Y Z, et al. Investigation on robust avalanche capacity of super-junction IGBT under UIS stress. IEEE Trans Electron Devices, 2024, 71(8), 4853 doi: 10.1109/TED.2024.3408774
[11]	Riccio M, Irace A, Breglio G, et al. Electro-thermal instability in multi-cellular Trench-IGBTs in avalanche condition: Experiments and simulations. 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, 2011, 124
[12]	Suzuki H, Ciappa M. TCAD simulation of current filamentation in adjacent IGBT cells under turn-on and turn-off short circuit condition. Microelectron Reliab, 2015, 55(9/10), 1976
[13]	Shankar B, Zeng K, Gunning B, et al. Movement of current filaments and its impact on avalanche robustness in vertical GaN P-N diode under UIS stress. 2022 Device Research Conference (DRC), 2022, 1
[14]	Endo K, Chinone N, Nakamura T, et al. Single-pulse observation of photoemission during avalanche breakdown in insulated gate bipolar transistor. Microelectron Reliab, 2020, 114, 113739 doi: 10.1016/j.microrel.2020.113739
[15]	Breglio G, Irace A, Napoli E, et al. Detection of localized UIS failure on IGBTs with the aid of lock-in thermography. Microelectron Reliab, 2008, 48(8/9), 1432
[16]	Suwa T. 2D-TCAD simulation study of capture layer and repellent layer of current filament in trench-gate IGBTs. 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, 32
[17]	Breglio G, Irace A, Napoli E, et al. Experimental detection and numerical validation of different failure mechanisms in IGBTs during unclamped inductive switching. IEEE Trans Electron Devices, 2013, 60(2), 563 doi: 10.1109/TED.2012.2226177
[18]	Shoji T, Ishiko M, Fukami T, et al. Investigations on current filamentation of IGBTs under undamped inductive switching conditions. Proceedings of ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005, 227
[19]	Tanaka M, Abe N, Nakagawa A. Impact of 3D simulation on the analysis of unclamped inductive switching. Jpn J Appl Phys, 2020, 59, SGGD01
[20]	Spirito P, Breglio G, Irace A, et al. Physics of the negative resistance in the avalanche $I {-} V$ curve of field stop IGBTs: Collector design rules for improved ruggedness. IEEE Trans Electron Devices, 2014, 61(5), 1457 doi: 10.1109/TED.2014.2311169
[21]	Spirito P, Maresca L, Riccio M, et al. Effect of the collector design on the IGBT avalanche ruggedness: A comparative analysis between punch-through and field-stop devices. IEEE Trans Electron Devices, 2015, 62(8), 2535 doi: 10.1109/TED.2015.2442334
[22]	Tong X, Liu S Y, Sun W F, et al. Complete avalanche process and failure mechanism of trench-gate FS-IGBT under unclamped inductive switching by using infrared visualization method. IEEE Trans Electron Devices, 2020, 67(9), 3908 doi: 10.1109/TED.2020.3011644
[23]	Bao X K, Zhu A K, Chen R T, et al. Voltage-balanced behavioral model considering carrier extraction effect for series-connected trench gate FS-IGBTs. 2022 IEEE International Power Electronics and Application Conference and Exposition (PEAC), 2022, 566

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Received: 07 February 2025 Revised: 12 March 2025 Online: Accepted Manuscript: 31 March 2025

Article Navigation > Journal of Semiconductors > 2025 > Accepted Manuscript

Jingping Zhang, Houcai Luo, Huan Wu, Bofeng Zheng, Xianping Chen. Dynamic avalanche reliability enhancement of FS-IGBT under unclamped inductive switching[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/25020006 ****J P Zhang, H C Luo, H Wu, B F Zheng, and X P Chen, Dynamic avalanche reliability enhancement of FS-IGBT under unclamped inductive switching[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/25020006

Citation:

Jingping Zhang, Houcai Luo, Huan Wu, Bofeng Zheng, Xianping Chen. Dynamic avalanche reliability enhancement of FS-IGBT under unclamped inductive switching[J]. Journal of Semiconductors, 2025, In Press. doi: 10.1088/1674-4926/25020006 ****

J P Zhang, H C Luo, H Wu, B F Zheng, and X P Chen, Dynamic avalanche reliability enhancement of FS-IGBT under unclamped inductive switching[J]. J. Semicond., 2025, accepted doi: 10.1088/1674-4926/25020006

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Dynamic avalanche reliability enhancement of FS-IGBT under unclamped inductive switching

DOI: 10.1088/1674-4926/25020006

CSTR: 32376.14.1674-4926.25020006

1.
Key Laboratory of Optoelectronic Technology & Systems, Chongqing University, Chongqing, China
2.
Key Laboratory of Power Transmission Equipment & System Security and New Technology, Chongqing University, Chongqing, China

More Information

Corresponding author: xianpingchen@cqu.edu.cn
Received Date: 2025-02-07
Revised Date: 2025-03-12

Available Online: 2025-03-31

Abstract

Abstract

The dynamic avalanche effect is a critical factor influencing the performance and reliability of the field-stop insulated gate bipolar transistors (FS-IGBT). Unclamped inductive switching (UIS) is the primary method for testing the dynamic avalanche capability of FS-IGBTs. Numerous studies have demonstrated that factors such as device structure, avalanche-generating current filaments, and electrical parameters influence the dynamic avalanche effect of the FS-IGBT. However, few studies have focused on enhancing the avalanche reliability of the FS-IGBT by adjusting circuit parameters during operation. In this paper, the dynamic avalanche effect of the FS-IGBT under UIS conditions is comprehensively investigated through a series of comparative experiments with varying circuit parameters, including bus voltage V_DC, gate voltage V_G, gate resistance R_g, load inductance L, and temperature T_C. Furthermore, a method to enhance the dynamic avalanche reliability of the FS-IGBT under UIS by optimizing circuit parameters is proposed. In practical applications, reducing gate voltage, increasing load inductance, and lowering temperature can effectively improve the dynamic avalanche capability of the FS-IGBT.
- FS-IGBT,
- dynamic avalanche,
- UIS,
- reliability,
- circuit parameters.

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