| Citation: |
Qian Qinsong, Li Haisong, Sun Weifeng, Yi Yangbo. Layout and process hot carrier optimization of HV-nLEDMOS transistor[J]. Journal of Semiconductors, 2009, 30(3): 034004. doi: 10.1088/1674-4926/30/3/034004
****
Qian Q S, Li H S, Sun W F, Yi Y B. Layout and process hot carrier optimization of HV-nLEDMOS transistor[J]. J. Semicond., 2009, 30(3): 034004. doi: 10.1088/1674-4926/30/3/034004.
|
Layout and process hot carrier optimization of HV-nLEDMOS transistor
DOI: 10.1088/1674-4926/30/3/034004
-
Abstract
Two layout and process key parameters for improving high voltage nLEDMOS (n-type lateral extended drain MOS) transistor hot carrier performance have been identified. Increasing the space between Hv-pwell and n-drift region and reducing the n-drift implant dose can dramatically reduce the device hot carrier degradations, for the maximum impact ionization rate near the Bird Beak decreases or its location moves away from the Si/SiO2 interface. This conclusion has been analyzed in detail by using the MEDICI simulator and it is also confirmed by the test results.-
Keywords:
- nLEDMOS
-
References
-
Proportional views
DownLoad: