Citation: |
Yan Xiaozhou, Kuang Xiaofei, Wu Nanjian. A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction[J]. Journal of Semiconductors, 2009, 30(4): 045007. doi: 10.1088/1674-4926/30/4/045007
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Yan X Z, Kuang X F, Wu N J. A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction[J]. J. Semicond., 2009, 30(4): 045007. doi: 10.1088/1674-4926/30/4/045007.
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A fast-settling frequency-presetting PLL frequency synthesizer with process variation compensation and spur reduction
DOI: 10.1088/1674-4926/30/4/045007
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Abstract
This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixed-signal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital pro-cessor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-Nsynthesizer with 1 MHz reference input was imple-mented in a 0.18μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 s, and the phase noise is –108 dBc/Hz @ 1 MHz. The reference spur is –52 dBc. -
References
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