SEMICONDUCTOR INTEGRATED CIRCUITS
Zheng Yongzheng, Li Weinan, Xia Lingli, Huang Yumei and Hong Zhiliang
Abstract: A fully integrated phase-locked loop (PLL) is presented for a single quadrature output frequency of 3.96 GHz. The proposed PLL can be applied to mode-1 MB-OFDM UWB hopping carrier generation. An adaptive frequency calibration loop is incorporated into the PLL. The capacitance area in the loop filter is largely reduced through a capacitor multiplier. Implemented in a CMOS process, this PLL draws 13.0 mA current from a single 1.2 V supply while occupying 0.55 mm2 die area.Measurement results show that the PLL achieves a phase noise of –70 dBc/Hz at 10 kHz offset and –113 dBc/Hz at 1 MHz offset. The integrated RMS jitter from 1 kHz to 10 MHz is 2.2 ps. The reference spur level is less than –68 dBc.
Key words: phase-locked loop, adaptive frequency calibration, loop ?lter, CMOS, UWB
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Received: 18 August 2015 Revised: 02 February 2009 Online: Published: 01 July 2009
| Citation: |
Zheng Yongzheng, Li Weinan, Xia Lingli, Huang Yumei, Hong Zhiliang. A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation[J]. Journal of Semiconductors, 2009, 30(7): 075003. doi: 10.1088/1674-4926/30/7/075003
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Zheng Y Z, Li W N, Xia L L, Huang Y M, Hong Z L. A 3.96 GHz phase-locked loop for mode-1 MB-OFDM UWB hopping carrier generation[J]. J. Semicond., 2009, 30(7): 075003. doi: 10.1088/1674-4926/30/7/075003.
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